Keynote And Plenary Speakers

Abstract: The next information technology architecture change will be to what has been called edge and endpoint devices, machine to machine communication or the internet of things (IoT). This change will be characterised by an explosion of data and the collection devices needed to store and process this data. With the bulk of data continuing to be stored on hard disk drives, the ability to secure and use this vast amount of data will become critical. In this talk, we’ll share on how the drive architecture needs to evolve to meet these security challenges as well as solutions to support this transition from Mobile/Cloud to Edge/Endpoint as we transition to Industry 4.0.

Biography: Mark Re is Chief Technology Officer and Senior Vice President of Research and Development at Seagate Technology. He is responsible for driving research on new technologies while also overseeing the hard disk drive component research and development teams. Over the course of a 14 years career at Seagate, Re has held many different leadership roles, including: SVP of R&D Media, Media Operations, Design Centers, and Heads R&D.

Prior to joining Seagate, Re served as SVP of Research and Development at Read-Rite in Fremont, California. Earlier career highlights include management positions at IBM in San Jose, California, and Yorktown Heights, New York, where Re’s primary focus was magnetic recording heads. During this time, Re was named an IBM Distinguished Engineer in 1997.

Re holds a Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University and a bachelor’s degree from Northwestern University.

Abstract: Years of Qualcomm research have resulted in innovative on-design cognitive technologies like machine learning and computer vision. They enable our devices to get to know our patterns and behaviors over time. Acting as natural human extensions, they have the ability to listen, recognize and respond/react more intuitively. The keynote addresses 3 aspects of what we bucket under “smart device”, viz. perception, inferencing and actuation and showcase a road towards having a smart, connected and secure community with advances in mobile ecosystem. It will be a combination of hardware platform in form of a different neural processing architecture that will provide dramatically increasing performance per watt (as the requirements for AI compute increase) along with software platform for execution of deep neural networks on device, 5G low latency connectivity and enhanced security layer.

Biography: Sachidanand is Vice-President, Engineering at Qualcomm Bangalore Design Center. Currently, he leads the Qualcomm HW engineering in India and is responsible for delivering HW products. At Qualcomm Sachi was responsible for productizing more than 60 designs. He has driven several innovative initiatives in different areas of HW design apart from delivering world class products. Prior to Qualcomm, Sachidanand worked for companies like Texas Instruments, Intel and Synopsys in the areas of Full Chip Integration and convergence, High Speed Circuit Synthesis, Design Automation and developing STA tools. He has an ME (ECE) from Indian Institute of Science (IISc), an MS (CE) from University of Louisiana, Lafayette, and a BSc (Physics) from Sri Sathya Sai Institute of Higher Learning.

Abstract: Though power consumption of transistors has steadily decreased, power density is currently the most limiting design factor for many kinds of embedded on-chip systems. Negative side effect of high power densities is a significantly decreased level of reliability. Though this general interdependency is known for long time, a precise quantification of this interdependency did not yet exist. This talk presents the newest findings in circuit aging mechanisms that for the first time allow drawing an accurate design space that comprises all relevant parameters and their interdependencies. Given this design space, guard-bands can be designed more carefully and system-level decisions can better exploit the trade-off between performance, power and circuit lifetime. The talk shows that these findings open new, not-yet-explored optimization potential for embedded on-chip systems.

Biography: Joerg Henkel (M’95-SM’01-F’15) received the master’s and PhD (Summa cum laude) degrees from the Technical University of Braunschweig, Germany. He is with the Karlsruhe Institute of Technology (KIT), Germany. Before he worked at the NEC Laboratories, Princeton, NJ. His current research interests include design and architectures for embedded systems with focus on low power and reliability. He has received various research awards, among them the 2008 DATE Best Paper Award, the 2009 IEEE/ACM William J. Mc Calla ICCAD Best Paper Award, the CODES+ISSS 2011, 2014 and 2015 Best Paper Awards. He was the general chair of major CAD events incl. ICCAD and ESWeek. He is the chairman of the IEEE Computer Society, Germany Section, and was the editor-in-chief of the ACM Transactions on Embedded Computing Systems for two terms. He is currently the editor-in-chief of the IEEE Design and Test Magazine. He is also an Initiator and Spokesperson of the national priority program on Dependable Embedded Systems of the German Science Foundation and the site coordinator (Karlsruhe site) of the three-university collaborative research center on invasive computing. He is a Fellow of the IEEE and holds ten US patents.

Abstract: The increasing demands to move, store and process data are bringing about a new shift in network topology. As the cloud continues to grow in significance, these new demands will push processing and storage towards the network edge. In this talk we will touch upon fog vs edge computing and review the reasons  how fog and edge computing are taking on increased significance and the impact  these have on the ecosystem. Finally, we will look at the latest wireless standard to address the movement of data at the edge.

Biography: Tim Donovan is Vice President, Wireless Engineering at Marvell Semiconductor, Inc. Mr. Donovan has been at Marvell over 17 years and has held many different leadership roles, working on a variety of wireless and multimedia technologies. Prior to Marvell, Mr. Donovan worked for a variety of companies in video signal processing semiconductor and product development. He holds 50 US patents.
Mr. Donovan obtained his MSEE from Illinois Institute of Technology and his BSEE from Marquette University.

Abstract: A transformation of agriculture reached commercial reality at the beginning of this century as automated steering of agricultural machine systems increased the productivity and convenience in crop production systems.  Following guidance, additional technologies have resulted in increasing optimized machine productivity.   Today, integrated worksite solutions through machine and information management continues to transform agriculture.  This is the precursor to autonomous worksite solutions that lead to the optimization of the worksite ecosystem.  This key note will review the progress from the perspective of the customer value provided by increasing automated systems and the industry execution of autonomous driving technologies and will enable the pathways to autonomous worksites.

Biography: Dr. Reid came to Deere and Company in January 2001 after a 14-year career at the University of Illinois where he was recognized internationally for his contributions in automation and control for off-road equipment.  Reid’s expertise includes machine vision perception, controls, and hardware-in-the-loop design.  Previously, Reid served as a consultant to agricultural and food industries in their effort to deploy advanced technologies into precision agriculture and systems automation.

Dr. Reid has been a deep technical expert and transformational leader in a number of off-road technology areas. This development of his expertise began in in the 1980’s with his PhD work on the Development of Computer Vision Algorithms for Agricultural Vehicle Guidance, and continued into the 1990’s with the research development of some of the first large-scale autonomous systems in agriculture. Once he arrived at Deere in 2000, Dr. Reid led Field Robotics for the Enterprise, and during this early period the Enterprise Field Robotics community developed from a group of unconnected and unleveraged projects to an Enterprise team that built very distinct and valuable capabilities. These capabilities included perception engineers, path and mission planning, and autonomous vehicle architecture. He also led and supported a number of incubation projects for autonomous operations.

In 2006 Dr. Reid moved into a new Enterprise position, Director, Product Technology and Innovation, in which he provided transformational Innovation Delivery Leadership. There have been several initiatives that John Reid has been active in leading, supporting, and executing, such as the Enterprise Technology Strategy, and the Global Technology Innovation Advisory Council. The latter led to the Enterprise Electronics Strategy, the Accelerated Innovation Process, the Innovation Sphere Strategy, the Enterprise Innovation and Collaboration Recognition, Global University Relationship Strategy, John Deere Fellow Program, Partnering for Innovation, and the approach to building the Global Technology Innovation Network (GTIN). Additionally Dr. Reid led Strategic Innovation Roadmaps for the Enterprise, and the transition to the focus on Game-Changing Innovation projects.

Abstract: Advances in microfluidics have led to the emergence of biochips for automating laboratory procedures in molecular biology. These devices enable the precise control of nano-litre volumes of biochemical samples and reagents. As a result, new biomedical applications and markets (e.g., high-through-out DNA sequencing, portable and point-of-care clinical diagnostics, and protein crystallization for drug discovery) are opening up for integrated circuits and miniaturized electronic systems.

This keynote will first introduce digital microfluidic biochips based on electro-wetting-on-dielectric, describe market drivers such as DNA sequencing and clinical diagnostics, and highlight recent commercialization success stories. The audience will next learn about design automation and dynamic reconfiguration aspects of microfluidic biochips. Synthesis tools will be described to map assay protocols from the lab bench to a droplet-based microfluidic platform and generate an optimized schedule of bioassay operations, the binding of assay operations to functional units, and the layout and droplet-flow paths for the biochip. The role of the digital microfluidic platform as a “programmable and reconfigurable processor” for biochemical applications will be highlighted. The speaker will also describe sensor-driven on-chip error recovery through cyber-physical system integration.

Finally, the speaker will highlight recent advances in utilizing cyber-physical integration for quantitative gene-expression analysis and single-cell analysis. This framework is an attempt to cross the formidable barrier that separates biochip engineering from mainstream microbiology research. Today’s microfluidics design-automation (“synthesis”) techniques do a lot more than on-chip droplet manipulation; they incorporate the myriad complexities of biomolecular protocols and they are therefore expected to make a positive impact on biochemistry/microbiology research.

Biography: Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the William H. Younger Distinguished Professor and Chair of the Department of Electrical and Computer Engineering and Professor of Computer Science at Duke University. Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award (2015), the ACM Transactions on Design Automation of Electronic Systems Best Paper Award (2017), and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award (2015), the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2017), and the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur (2014). He is a Research Ambassador of the University of Bremen (Germany) and a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany. He has held Visiting Professor positions at University of Tokyo and the Nara Institute of Science and Technology (NAIST) in Japan, and Visiting Chair Professor positions at Tsinghua University (Beijing, China) and National Cheng Kung University (Tainan, Taiwan).

Prof. Chakrabarty’s current research projects include: testing and design-for-testability of integrated circuits and systems; microfluidic biochips; hardware security; data analytics for fault diagnosis and failure prediction; neuromorphic computing systems. He is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He was a 2009 Invitational Fellow of the Japan Society for the Promotion of Science (JSPS). He is a recipient of the 2008 Duke University Graduate School Dean’s Award for excellence in mentoring, and the 2010 Capers and Marion McDonald Award for Excellence in Mentoring and Advising, Pratt School of Engineering, Duke University. He has served as a Distinguished Visitor of the IEEE Computer Society (2005-2007, 2010-2012), a Distinguished Lecturer of the IEEE Circuits and Systems Society (2006-2007, 2012-2013), and an ACM Distinguished Speaker (2008-2016).

Prof. Chakrabarty served as the Editor-in-Chief of IEEE Design & Test of Computers during 2010-2012 and ACM Journal on Emerging Technologies in Computing Systems during 2010-2015. Currently he serves as the Editor-in-Chief of IEEE Transactions on VLSI Systems. He is also an Associate Editor of IEEE Transactions on Biomedical Circuits and Systems, IEEE Transactions on Multiscale Computing Systems, and ACM Transactions on Design Automation of Electronic Systems.

Abstract: Traditionally, there has been a division of labor between computers and humans where all forms of number crunching and bit manipulation are left to computers, whereas intelligent decision-making is left to us humans. We are now at the cusp of a major transformation that can disrupt this balance. This disruption is triggered by an unprecedented convergence of massive compute with massive data, and some recent algorithmic advances. This confluence has the potential to spur a virtuous cycle of compute. It can significantly impact how we do computing and what computing can do for us. In this talk I will discuss some of the application-level opportunities and system-level challenges that lie at the heart of this intersection of traditional high-performance computing with emerging data-intensive computing.

Biography: Pradeep Dubey is an Intel Fellow and Director of Parallel Computing Lab (PCL), part of Intel Labs. His research focus is computer architectures to efficiently handle new compute- and data-intensive application paradigms for the future computing environment. Dubey previously worked at IBM’s T.J. Watson Research Center, and Broadcom Corporation. He has made contributions to the design, architecture, and application-performance of various microprocessors, including IBM® Power PC*, Intel® i386TM, i486TM, Pentium® Xeon®, and the Xeon Phi™ line of processors. He holds over 36 patents, has published over 100 technical papers, won the Intel Achievement Award in 2012 for Breakthrough Parallel Computing Research, and was honored with Outstanding Electrical and Computer Engineer Award from Purdue University in 2014. Dr. Dubey received a PhD in electrical engineering from Purdue University. He is a Fellow of IEEE.

Abstract: In the last couple of years, IoT, Automotive, Cloud have become very popular buzz words. In connection with these applications, “Safety” and “Security” get a lot of attention. The entire value chain of Systems is rapidly evolving to create new architectures. These new architectures create enhanced needs to create massively heterogeneous systems. Concerns about cyber-attacks and security in such a connected and complex environment are well-justified. System designers need to worry about security at all levels, from the legitimacy of the SoC through the data communication channels, and everything in between.

This session will address the latest trends enabling consolidation opportunities, potential security exposures that system designers must consider in complex heterogeneous environments, and software and hardware solutions available to separate and secure critical system components.

Biography: Ruchir has close to 20 years of experience in the semiconductor industry focused having executed at multiple levels of responsibilities in design and development of ASIC, FPGA and PCB products. In all these years, Ruchir has either directly worked on or worked with customers on over 200 IC Tapeouts.
After spending close to 10 years in the IC development roles, Ruchir moved into EDA and Applications. In this role Ruchir has held various leadership roles. In these roles, Ruchir has worked with many customers world-wide and helped them to define the problem and then work to create solutions. Ruchir spent 11 years in Mentor, US and then moved to India in 2005 to start building the application engineering team in India.
Until recently, Ruchir was leading a global team on DFT and Analog/Mixed Signal technologies. Now, Ruchir leads the India technical organization that works with customers across all product lines of Mentor.
Ruchir graduated from Wayne State University, Michigan with a Masters in Computer Engineering and has an undergraduate degree in Electronics & Instrumentation from Indore University, India.

Abstract: “This talk starts by looking at the intersection of two rapidly developing fields.  The first is research into the structure and function of the brain, as exemplified by the Brain Initiatives of governments, and research organizations such as the Allen Brain Institute, the Howard Hughes Medical Institute, and the Max Planck Society.  The second is the Internet of Things, allowing low cost, real time monitoring of many aspects of our environment and lives.  We look at existing and proposed methods of brain research with an eye on which ones could be adapted to the Internet of Things.  The implications are many and various, ranging from the good (early detection and treatment of neurological disease), to the bad (violations of privacy and civil liberties), and the ugly (advertising and propositions targeted to those most vulnerable).  New questions of engineering ethics will arise, as machines will surely deduce facts about us that are currently private or not known even to ourselves, and we must decide as a society how this information is to be treated.”

Biography: Lou Scheffer received his BS and MS degrees in EE from Caltech, and a PhD. In 1983 from Stanford University.  Professionally, he performed IC design for HP, followed by IC CAD software development at HP, then Valid, then Cadence.  During this time he was an editor of IEE Transactions on CAD, a member of the Board of Governors of IEEE, and program, technical and general chair of the conferences ICCAD, TAU, ISPD, and SLIP.  In 2008, Lou switched fields to biology, where he now studies  the structure and function of the brain.  Working at the Howard Hughes Medical Institute, Lou is part of an effort using electron microscopy to reconstruct the detailed structure and function of the brain, starting with the fruit fly, Drosophila.  Lou is the author of numerous papers on EE, physics, SETI, and biology, the author of two books, and holds 35 patents.