Logic and Physical synthesis, Place & Route, Clock Tree Synthesis,
Physical Verification, Static/Dynamic Timing, Signal integrity, xOCV, DFM/DFY,
Physical Design for Debug

 Analog Mixed Signal IP, High-Speed Interfaces, Various RAM design, IO Buffer,PLL/DLL Design, Standard Cell Design

 FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping

Digital/Analog Power Optimization Techniques, Power Architectures, Power/Performance Trade Off, Power Delivery Network, Power Switch, Power/Thermal Balance

Verification and Test: Design for Test (DFT), Product Level Test, Design Verification Techniques, Mixed Signal Verification, Fault Tolerance, DPPM Betterment, Formal Verification, Emulation

Regulator Design, On Chip Regulator, RF Circuits, Effective Spectrum Utilization, New Transceiver Design in 5G Era, RF Certification, LDO Design, SMPS Design

Simulation Tools for Design Verification, SPICE Simulation,Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verification Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal Simulations

Nano-CMOS Technologies, MEMS, CMOS Sensors, CAD/EDA Methodologies for Nanotechnology, Nano-Electronics and NanoCircuits, Nano-Sensors, MEMS Applications, Nano-Assemblies and Devices, NonClassical CMOS; Post-CMOS Devices; Biomedical Circuits, Carbon Nano-Tubes Based Computing

ESL, System-level design methodology, Processor and memory design, Concurrent  interconnect, Networks-on-chip, Defect Tolerant Architectures, Hardware/Software Co-Design & Verification, Reconfigurable Computing, Embedded Multicores SOC and Systems,Embedded Software Including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip

Deep Neural Network, CNN, Computer Vision, On chip Neural Processing Engines, ML Algorithms

Platform Architectures, Chip Partitioning, Power Management, Board Level Design, Packaging, Signal Integrity, Power/Thermal Trade Off

Server Processor Architecture, Compute Efciency, Benchmark Enhancement, Edge Computing, Cloud Computing, Distributed Architecture, Heterogeneous Compute

Ethernet, Networking Algorithms, 5G, Communication Standards, LTE, Switching

HW Security Design, SW Security, Architectures, Algorithms

Simulation Tools for Design Verification, SPICE Simulation, Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verification Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal Simulations, Transistor Level Tools, EDA on Cloud

Silicon Technology Advancements, FinFET, Beyond FinFET, Transistor Level Performance Improvements, Device Microelectronics, Beyond Silicon, PVT Optimization, Design Optimization Corners, Yield Improvement, Post Tapeout Methodology