January 4 – 8 , 2020


@Leela Palace, Bengaluru




Over 50+ High Quality Sessions

The 33rd International Conference on VLSI Design & The 19th International Conference on Embedded Design is happening in Namma Bengaluru!

Sponsors- Industry









Banquet Keynote

Topic: Of Brains and Computers


Dr. Jan M. Rabaey


Dr. Max Shulaker

Keynote Speakers


Suk Lee


Dr. Yvain Thonnart

Sponsors - Industry & Academic Consortium

CPS published by logo
ieee cs
ieee bangalore

The Theme of the Conference is...

"Connecting Intelligent Systems to New Age Transistors"

Semiconductors have made real what our ancestors would consider magic. The convergence of technology with modern life has reached a state where dependence of human life on semiconductor technology is ubiquitous. Intelligent systems are revolutionizing a variety of industries to help improve energy efficiency, quality, and flexibility of systems. To achieve these superior experience massive amount of researches are ongoing in the field of algorithms, embedded HW/SW design, IP core design and SoCs. These are well backed up by govt policies, standards and industry forums.

Incredible demand on functionality in a chip in a given power/thermal envelope forcing transistor geometries go smaller which is imposing newer challenges in VLSI design and associated EDA tools/flows/methodologies. In 33rd International Conference of VLSI Design and 19th International Conference on Embedded Design, we plan to bring together all the leaders from industries, academia, industry bodies, government, standard organizations to go over all technology enablers in an “outside-in approach to design VLSI” which includes intelligent systems design, new techniques in algorithms, HW/SW/Protocol standards, core VLSI design, EDA tools/flows/methodologies and core silicon technologies


Efficient Component Design

  • Digital Design:

     Logic and Physical synthesis, Place & Route, Clock Tree Synthesis,
    Physical Verification, Static/Dynamic Timing, Signal integrity, xOCV, DFM/DFY,
    Physical Design for Debug

  • Analog Design:

     Analog Mixed Signal IP, High-Speed Interfaces, Various RAM design, IO Buffer,PLL/DLL Design, Standard Cell Design

  • FPGA:

     FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping

  • Power/Energy Efficiency:

    Digital/Analog Power Optimization Techniques, Power Architectures, Power/Performance Trade Off, Power Delivery Network, Power Switch, Power/Thermal Balance

  • Verification and Test:

    Verification and Test: Design for Test (DFT), Product Level Test, Design Verification Techniques, Mixed Signal Verification, Fault Tolerance, DPPM Betterment, Formal Verification, Emulation

  • Power Management and RF:

    Regulator Design, On Chip Regulator, RF Circuits, Effective Spectrum Utilization, New Transceiver Design in 5G Era, RF Certification, LDO Design, SMPS Design

  • Electronic Design Automation:

    Simulation Tools for Design Verification, SPICE Simulation,Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verification Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal Simulations

  • Emerging Technologies:

    Nano-CMOS Technologies, MEMS, CMOS Sensors, CAD/EDA Methodologies for Nanotechnology, Nano-Electronics and NanoCircuits, Nano-Sensors, MEMS Applications, Nano-Assemblies and Devices, NonClassical CMOS; Post-CMOS Devices; Biomedical Circuits, Carbon Nano-Tubes Based Computing

Intelligent System Design

  • Embedded Systems Design:

    ESL, System-level design methodology, Processor and memory design, Concurrent  interconnect, Networks-on-chip, Defect Tolerant Architectures, Hardware/Software Co-Design & Verification, Reconfigurable Computing, Embedded Multicores SOC and Systems,Embedded Software Including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip

  • Artificial Intelligence:

    Deep Neural Network, CNN, Computer Vision, On chip Neural Processing Engines, ML Algorithms

  • System Level Algorithms and Architectures:

    Platform Architectures, Chip Partitioning, Power Management, Board Level Design, Packaging, Signal Integrity, Power/Thermal Trade Off

  • High Performance Computing:

    Server Processor Architecture, Compute Efciency, Benchmark Enhancement, Edge Computing, Cloud Computing, Distributed Architecture, Heterogeneous Compute

  • Efficient Connectivity:

    Ethernet, Networking Algorithms, 5G, Communication Standards, LTE, Switching

  • Security: Security Protocols

    HW Security Design, SW Security, Architectures, Algorithms

New Age Transistors and Tools/Flows/Methodology

  • Electronic Design Automation:

    Simulation Tools for Design Verification, SPICE Simulation, Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verification Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal Simulations, Transistor Level Tools, EDA on Cloud

  • Transistor Level Design:

    Silicon Technology Advancements, FinFET, Beyond FinFET, Transistor Level Performance Improvements, Device Microelectronics, Beyond Silicon, PVT Optimization, Design Optimization Corners, Yield Improvement, Post Tapeout Methodology

About VLSID Conference

VLSI Design Conference started as a simple idea in 1985: to sense the level of VLSI activities in India with a focus on engineering education & research.

Over the years, the conference has grown equilaterally with a VLSI community that includes the likes of Multinational Industries, Academic contributors and Government bodies around the globe. With its global footprints VLSID is recognized as a ‘Sister Conference’ of Design Automation Conference. This conference is sponsored by VLSI Society of India (VSI).


Event Location

The Leela Palace

Address: 23, HAL Old Airport Rd, HAL 2nd Stage, Kodihalli, Bengaluru, Karnataka 560008

Phone: 080 2521 1234