http://embeddedandvlsidesignconference.org/  
CALL FOR PAPERS  
his joint conference is a forum for researchers and designers to present and discuss  
urrent topics in VLSI design, EDA, embedded systems, and emerging technologies. Two  
ays of tutorials (January 5-6) will be followed by three days (January 7-9) of regular  
aper sessions, special sessions, and embedded tutorials. The program will also include  
dustry sessions along with exhibits, panel discussions, design contest, and Ph.D.  
orum.  
TOPICS OF INTEREST  
egular papers are invited in all areas of VLSI design and embedded systems, including  
ut not limited to the following categories:  
d Systems  
Security & Privacy  
IoT and Cyber-Physical Systems  
Smart  
machine  
cognitive  
autonomous  
learning  
systems,  
techniques,  
artificial  
System-level design, HW/SW co-  
design, multi-core SoCs, embedded  
processor and memory design,  
networks-on-chip, defect-tolerant  
architectures, accelerators, FPGA  
Embedded systems security,  
hardware security, IP trust,  
physically unclonable functions,  
random number generators,  
fault tolerant systems and  
architectures, system security,  
side channel attacks and  
countermeasures  
Internet-of-Things (IoT) devices,  
cyber-physical systems, sensors,  
actuators, displays, control systems,  
and design for safety and  
certifications in airborne, health  
care, automotive & IoT applications  
systems,  
intelligence, machine learning for  
VLSI CAD, data analytics,  
neuromorphic and brain-inspired  
computing, and case studies.  
and  
parallelization,  
reconfigurable  
systems,  
virtualization,  
firmware, middleware, case studies.  
Power & Energy  
Test & Verification  
Design Automation Algorithms  
RF Design  
Low-power  
design,  
low-power  
Simulation, formal verification,  
validation at different abstraction  
levels, DFT, fault modelling and  
simulation, ATPG, BIST, fault  
tolerance, post-silicon validation and  
debug, delay test, memory test,  
reliability testing  
Logic and behavioral synthesis,  
logic mapping, simulation and  
RF IP design, low-power and high-  
speed RFICs, RF modeling and CAD  
simulation, RFIC technologies,  
circuits, devices, fabrication, testing,  
reliability, and packaging; synthesis  
and verification, noise analysis.  
systems, wireless power delivery,  
Power analysis and estimation,  
optimization and low-power design,  
energy-efficient design, thermal  
management, energy harvesting,  
approximate computing  
formal  
(partitioning,  
verification,  
layout  
placement,  
routing, floor planning, and  
compaction),  
optimizations  
post  
route  
Digital Design  
Analog Mixed Signal  
CMOS Technology and Devices  
Emerging Technologies  
Logic and physical synthesis, place  
and route, clock tree design, timing  
and signal integrity, design for  
manufacturability and yield, power  
integrity, variation-tolerant design  
Design of analog and mixed signal  
IPs, high-speed wired and wireless  
interfaces, low-power analog design,  
analog and mixed-signal modeling,  
synthesis and validation  
Deep nanoscale CMOS devices,  
Post-CMOS devices, MEMS sensors,  
biomedical circuits, lab-on-chip,  
silicon  
photonics, spintronics, memristors,  
neuromorphic/quantum computing  
device  
simulation,  
modelling and  
multi-domain  
carbon  
nanotubes,  
simulation, device/circuit-level  
reliability and variability  
THREE SPECIAL ISSUES  
S UBM ISSI ONS
Highest ranked papers from regular  
submissions will be invited to the thematic  
special issues of the following journals:  
All submissions should be made electronically via the conference website  
http://embeddedandvlsidesignconference.org/ by July 15, 2018. Your manuscript  
should clearly state the novel ideas, results, and applications of the contribution. Paper  
submissions will undergo a double-blind review. Papers must be in PDF format and not  
exceed 6 single-spaced pages including figures and references in two-column IEEE  
conference paper format (10pt font). Papers exceeding the page limit or identifying the  
authors will be rejected without review.  
BEST PAPER AWARDS  
Top papers will be considered for the Best Paper Award, Best Student Paper Award,  
and Honorable Mention Award.  
IEEE Transactions on VLSI Systems  
on security and privacy)  
(
IET Computers & Digital Techniques  
on energy-aware computing)  
(
IETE Journal of Research  
on machine learning, papers will be  
included in 1-2 issues)  
(