Technical Program Committee

Technical Program Commitee Chairs

Name of the member Affiliation
Sudeep Pasricha Colorado State University, United States
Rahul Rao IBM, India
Virendra Singh IIT Bombay, India

 

Technical Program Commitee Chairs

Name of the member Affiliation Tracks
Umit Ogras Arizona State University, United States committee:E1-E5: Embedded Systems
Anshul Kumar I.I.T. Delhi, India committee:E1-E5: Embedded Systems
Partha Pande Washington State University, United States committee:M1: System-level Design
Sourav Roy NXP committee:M1: System-level Design
Tsung-Yi Ho National Tsing Hua University, Taiwan committee:M2: Advances in Digital Design
Surhud Khare Intel Corporation, India committee:M2: Advances in Digital Design
Deukhyoun Heo Washington State University, United States committee:M3: Analog, Mixed-Signal,
and RF Design
Rajesh Zele IIT Bombay, India committee:M3: Analog, Mixed-Signal,
and RF Design
Preeti Ranjan Panda IIT Delhi, India committee:M4: Power-Aware Design
Vijaykrishnan Narayanan Penn State University, United States committee:M4: Power-Aware Design
Sudeb Dasgupta Associate Professor, IIT Roorkee, India committee:M5: CMOS Technology
and Devices
Bipin Rajendran New Jersey Institute of Technology,
United States
committee:M5: CMOS Technology
and Devices
Siddhartha Dattagupta Indian Institute of Technology Bombay, India committee:M6: Emerging Technologies
Mehdi Tahoori Karlsruhe Institute of Technology, Germany committee:M6: Emerging Technologies
Debdeep Mukhopadhyay Department of Computer Science
and Engineering,Indian Institute
of Technology Kharagpur, India
committee:S1-S3: Design for Safety
and Security
Swarup Bhunia University of Florida, United States committee:S1-S3: Design for Safety
and Security
Mostafa Taha Western University, Canada committee:S1-S3: Design for Safety and Security
Prabhat Mishra University of Florida, United States committee:T1: Design Verification
Masahiro Fujita University of Tokyo, Japan committee:T1: Design Verification
Rubin Parekhji Texas Instruments (India) Pvt. Ltd., India committee:T2: Test, Reliability,
and Fault-Tolerance
Adit Singh Auburn University, United States committee:T2: Test, Reliability,
and Fault-Tolerance
Srinivas Katkoori University of South Florida, United States committee:T3: Design Automation
and CAD Tools
Sridhar Rangarajan IBM India Pvt LTD., India committee:T3: Design Automation
and CAD Tools

 

Technical Program Commitee Chairs

Name of the member Affiliation Tracks
Mohammad Al Faruque University of California Irvine, United States E1-E5: Embedded Systems
Manu Awasthi Indian Institute of Technology Gandhinagar, India E1-E5: Embedded Systems
Paul Bogdan University of Southern California, United States E1-E5: Embedded Systems
Anupam Chattopadhyay Nanyang Technological University, Singapore E1-E5: Embedded Systems
Amol Dharangutte John Deere, India E1-E5: Embedded Systems
Gautam Hazari AMD India Private Limited, India E1-E5: Embedded Systems
Hrishikesh Jayakumar Qualcomm Inc., United States E1-E5: Embedded Systems
Younghyun Kim University of Wisconsin–Madison, United States E1-E5: Embedded Systems
Siew Kei Lam Nanyang Technological University, Singapore E1-E5: Embedded Systems
Hyung Gyu Lee Daegu University, Republic of Korea E1-E5: Embedded Systems
Kyoungwoo Lee Yonsei University, Republic of Korea E1-E5: Embedded Systems
Peter Marwedel TU Dortmund, Germany E1-E5: Embedded Systems
Amitava Mukherjee IBM India Private Limited, India E1-E5: Embedded Systems
Sri Parameswaran UNSW, Australia E1-E5: Embedded Systems
Karthick Parashar IMEC, Leuven, Belgium E1-E5: Embedded Systems
Jaehyun Park Arizona State University, United States E1-E5: Embedded Systems
Vishwanath Patil John Deere India Private Limited, India E1-E5: Embedded Systems
Zebo Peng Linkoping University, Sweden E1-E5: Embedded Systems
Debasri Saha A.K. Choudhury School of IT, University of Calcutta,
India
E1-E5: Embedded Systems
Vineet Sahula National Institute of Technology Jaipur, India E1-E5: Embedded Systems
Arnab Sarkar IIT Guwahati, India E1-E5: Embedded Systems
Muhammad Shafique Vienna University of Technology (TU Wien), Austria E1-E5: Embedded Systems
Aviral Shrivastava Arizona State University, United States E1-E5: Embedded Systems
Prashant Sohani NVIDIA Corporation, India E1-E5: Embedded Systems
Dey Soumyajit IIT Kharagpur, India E1-E5: Embedded Systems
Hiroyuki Tomiyama Ritsumeikan University, Japan E1-E5: Embedded Systems
Swagath Venkataramani IBM Corporation, United States E1-E5: Embedded Systems
Rangharajan Venkatesan NVIDIA Corporation, United States E1-E5: Embedded Systems
Wei Zhang Hong Kong University of Science and Technology,
Hong Kong Special Administrative Region of China
E1-E5: Embedded Systems
Niraj Jha Princeton University, United States E1-E5: Embedded Systems:M1:
System-level Design
Ishan Thakkar Colorado State University, United States E1-E5: Embedded Systems:M1:
System-level Design
Venkatnarayan Hariharan Intel Technology India Pvt. Ltd., India E1-E5: Embedded Systems:T3:
Design Automation and CAD Tools:
M3b: Analog, Mixed-Signal, and RF Design
Lava Bhargava Malaviya National Institute of Technology, India M1: System-level Design
Talal Bonny Electrical & Computer Engineering Dept,
University of Sharjah, United Arab Emirates
M1: System-level Design
Sujay Deb IIIT Delhi, India M1: System-level Design
Basant Dwivedi ARM, India M1: System-level Design
Amlan Ganguly Rochester Institute of Technology, United States M1: System-level Design
Joerg Henkel KIT, Germany M1: System-level Design
Hemangee Kapoor Indian Institute of Technology Guwahati, India M1: System-level Design
Turbo Majumder Intel Corporation, United States M1: System-level Design
Madhu Mutyam Indian Institute of Technology Madras, India M1: System-level Design
Smruti R. Sarangi IIT Delhi, India M1: System-level Design
Kamakoti V Professor, India M1: System-level Design
Mrugesh Walimbe Xilinx India Technology Services Pvt. Ltd., India M1: System-level Design
jason xue City University of Hong Kong, Hong Kong Special
Administrative Region of China
M1: System-level Design
Tiju Jacob Intel, India M1: System-level Design:M2:
Advances in Digital Design
Amit Patra Professor, India M1: System-level Design:M3b:
Analog, Mixed-Signal, and RF Design:
M6: Emerging Technologies
Joycee Mekie Indian Institute of Technology Gandhinagar, India M1: System-level Design:M5:
CMOS Technology and Devices
Rajesh Bhagwat Seagate, India M2: Advances in Digital Design
Utpal Desai Qualcomm, India M2: Advances in Digital Design
Prokash Ghosh NXP India Pvt Ltd, India M2: Advances in Digital Design
Gopal Iyer Intel Corporation, United States M2: Advances in Digital Design
Mark Po-Hung Lin National Chung Cheng University, Taiwan M2: Advances in Digital Design
Arijit Raychowdhury Georgia Institute of Technology, United States M2: Advances in Digital Design
Yiyu Shi University of Notre Dame, United States M2: Advances in Digital Design
Shigeru Yamashita Ritsumeikan University, Japan M2: Advances in Digital Design
Nitin Agarwal Texas Instruments, India M3: Analog, Mixed-Signal, and RF Design
Pawan Agarwal Maxlinear Inc, United States M3: Analog, Mixed-Signal, and RF Design
Sheikh Nijam Ali School of EECS, Washington State University,
United States
M3: Analog, Mixed-Signal, and RF Design
Debashis Banerjee Georgia Institute of Technology, United States M3: Analog, Mixed-Signal, and RF Design
Joe Baylon Washington State University, United States M3: Analog, Mixed-Signal, and RF Design
Tarun Bhattacharyya Indian Institute of Technology, India M3: Analog, Mixed-Signal, and RF Design
Erfan Ghaderi Washington State University, United States M3: Analog, Mixed-Signal, and RF Design
Srinivasan Gopal Washington State university, United States M3: Analog, Mixed-Signal, and RF Design
Shalabh Gupta IIT Bombay, India M3: Analog, Mixed-Signal, and RF Design
Dr. Manas Kumar Hati IIT Kharagpur, Kharagpur, India M3: Analog, Mixed-Signal, and RF Design
Wookpyo Hong Washington State University, United States M3: Analog, Mixed-Signal, and RF Design
Huan Hu Washington State University, United States M3: Analog, Mixed-Signal, and RF Design
Jaeyoung Jung Qualcomm, United States M3: Analog, Mixed-Signal, and RF Design
Sougata Kumar Kar Nanyang Technological University, Singapore M3: Analog, Mixed-Signal, and RF Design
Vishal Khatri IBM, Bangalore, India M3: Analog, Mixed-Signal, and RF Design
Sudip Kundu BIT MESRA, RANCHI, India M3: Analog, Mixed-Signal, and RF Design
Debashis Mandal Post Doctoral Research Scholar, Arizona
State University, United States
M3: Analog, Mixed-Signal, and RF Design
Bai Nguyen Washington State University, United States M3: Analog, Mixed-Signal, and RF Design
Soumya Pandit Institute of Radio Physics and Electronics,
University of Calcutta, India
M3: Analog, Mixed-Signal, and RF Design
Arya Rahimi Washington State University, United States M3: Analog, Mixed-Signal, and RF Design
Sudip Roy IIT Roorkee, India M3: Analog, Mixed-Signal, and RF Design
Bibhu Datta Sahoo University of Illinois at Urbana-Champaign,
United States
M3: Analog, Mixed-Signal, and RF Design
Shreyas Sen ECE, Purdue University, United States M3: Analog, Mixed-Signal, and RF Design
mrigank sh iit kgp, India M3: Analog, Mixed-Signal, and RF Design
Nithin Shastri NITG, India M3: Analog, Mixed-Signal, and RF Design
Maryam Shojaei Baghini Department of Electrical Engg., IIT-Bombay, India M3: Analog, Mixed-Signal, and RF Design
Vineet Singh University of Texas at Austin, United States M3: Analog, Mixed-Signal, and RF Design
nijwm wary Indian Institue of Technology, Kharagpur, India M3: Analog, Mixed-Signal, and RF Design
Xinmin Yu Qualcomm Technologies Inc., United States M3: Analog, Mixed-Signal, and RF Design
Zhiyuan Zhou Washington State University, United States M3: Analog, Mixed-Signal, and RF Design
Subhanshu Gupta School of EECS, Washington State University,
United States
M3: Analog, Mixed-Signal, and RF Design
Anand Bulusu Indian Institute of Technology Roorkee, India M3: Analog, Mixed-Signal, and RF Design
Rajat Subhra Chakraborty Assistant Professor, Computer Science and,
Engineering, IIT Kharagpur, India
M3: Analog, Mixed-Signal, and RF Design
Vivek De Intel Corporation, United States M4: Power-Aware Design
Arun Joseph IBM, India M4: Power-Aware Design
Rajiv Joshi IBM, United States M4: Power-Aware Design
Duo Liu Chongqing University, China M4: Power-Aware Design
Nagi Naganathan Avago Technologies, United States M4: Power-Aware Design
Aryabartta Sahu CSE, IIT Guwahati, India M4: Power-Aware Design
Mingoo Seok Columbia University, United States M4: Power-Aware Design
Charles Augustine Intel Circuit Research Lab, United States M5: CMOS Technology and Devices
Parthasarathi Chakrabarti Department of Electronics Engineering, IIT(BHU),
Varanasi, India
M5: CMOS Technology and Devices
Yogesh Chauhan IIT Kanpur, India M5: CMOS Technology and Devices
Deepanjan Datta GLOBALFOUNDRIES Engineering Private Limited,
India
M5: CMOS Technology and Devices
Veeresh Deshpande IBM Research GmbH, Switzerland M5: CMOS Technology and Devices
Abhishek Dixit Department of Electrical Engineering, IIT Delhi,
India
M5: CMOS Technology and Devices
Ankur Gupta Assistant Professor, India M5: CMOS Technology and Devices
Shreepad Karmalkar IIT Madras, India M5: CMOS Technology and Devices
Abhinav Kranti Indian Institute of Technology Indore, India M5: CMOS Technology and Devices
Santanu Mahapatra M5: CMOS Technology and Devices
Nihar Mohapatra Associate Professor, India M5: CMOS Technology and Devices
Deleep Nair IIT Madras M5: CMOS Technology and Devices
Chandan Kumar Sarkar Jadvpur University, India M5: CMOS Technology and Devices
Manan Suri IIT-Delhi, India M5: CMOS Technology and Devices
santosh vishvakarma Indian Institute of technology Indore, India M5: CMOS Technology and Devices
Rajendra Patrikar VNIT, India M5: CMOS Technology and Devices:
M6: Emerging Technologies
Yiran Chen University of Pittsburgh, United States M6: Emerging Technologies
Dhireesha Kudithipudi Rochester Institute of Technology, United States M6: Emerging Technologies
Dimin Niu Samsung Semiconductor Inc., United States M6: Emerging Technologies
Yaojun Zhang Everspin Technologies., United States M6: Emerging Technologies
Santosh Balasubramanian IBM, India S1-S3: Design for Safety and Security
Mainak Banga Intel Corporation, United States S1-S3: Design for Safety and Security
Chip Hong Chang Nanyang Technological University, Singapore S1-S3: Design for Safety and Security
Yier Jin University of Florida, United States S1-S3: Design for Safety and Security
Robert Karam University of South Florida, United States S1-S3: Design for Safety and Security
Ramesh Karri NYU, United States S1-S3: Design for Safety and Security
Bodhisatwa Mazumdar IIT Indore, India S1-S3: Design for Safety and Security
Seetharam Narasimhan Intel Corp, United States S1-S3: Design for Safety and Security
Goutam Paul Indian Statistical Institute, India S1-S3: Design for Safety and Security
Sandip Ray NXP Semiconductors, United States S1-S3: Design for Safety and Security
Chester Rebeiro Assistant Professor, IIT Madras, India S1-S3: Design for Safety and Security
Bijan Alizadeh University of Tehran, Iran (Islamic Republic of) T1: Design Verification
Kanad Basu NYU, United States T1: Design Verification
Mingsong Chen East China Normal University, China T1: Design Verification
Pallab Dasgupta Indian Institute of Technology Kharagpur, India T1: Design Verification
Rolf Drechsler University of Bremen/DFKI, Germany T1: Design Verification
Amir Masoud Gharehbaghi The University of Tokyo, Japan T1: Design Verification
Aritra Hazra Dept of CSE, IIT Kharagpur, India T1: Design Verification
Graziano Pravadelli University of Verona, Italy T1: Design Verification
Shobha Vasudevan UIUC, United States T1: Design Verification
Andreas Veneris University of Toronto, Canada T1: Design Verification
Robert Wille Johannes Kepler University Linz, Austria T1: Design Verification
Abhijit Chatterjee Georgia Tech, United States T2: Test, Reliability, and Fault-Tolerance
Santanu Chattopadhyay IIT Kharagpur, India T2: Test, Reliability, and Fault-Tolerance
Vivek Chickermane CADENCE, United States T2: Test, Reliability, and Fault-Tolerance
Chethan Kumar Y.B. Texas Instruments, India T2: Test, Reliability, and Fault-Tolerance
Huawei Li Institute of Computing Technology, Chinese
Academy of Sciences, China
T2: Test, Reliability, and Fault-Tolerance
Nagesh Tamarapalli AMD, India T2: Test, Reliability, and Fault-Tolerance
Devanathan VR Texas Instruments Inc., United States T2: Test, Reliability, and Fault-Tolerance
Xiaoqing Wen Kyushu Institute of Technology, Japan T2: Test, Reliability, and Fault-Tolerance
Vishwani Agrawal Auburn University, United States T2: Test, Reliability, and Fault-Tolerance:
M4: Power-Aware Design:M5: CMOS Technology
and Devices
Bhargab Bhattacharya Indian Statistical Institute, Kolkata, India T2: Test, Reliability, and Fault-Tolerance:
T3: Design Automation and CAD Tools
Siddharth Garg University of Waterloo, Canada T2: Test, Reliability, and Fault-Tolerance:
T3: Design Automation and CAD Tools
Ansuman Banerjee Indian Statistical Institute, India T3: Design Automation and CAD Tools
Alex Doboli State University of New York at Stony Brook,
United States
T3: Design Automation and CAD Tools
Swaroop Ghosh Pennsylvania State University, United States T3: Design Automation and CAD Tools
Amey Kulkarni University of Maryland, Baltimore County, United States T3: Design Automation and CAD Tools
Arijit Mondal IIT Patna, India T3: Design Automation and CAD Tools
Sachin Patkar Professor, Dept. EE, IIT Bombay, Mumbai, India T3: Design Automation and CAD Tools
sree hari rao patri NIT WARANGAL, India T3: Design Automation and CAD Tools
Somyendu Raha Indian Institute of Science, India T3: Design Automation and CAD Tools
Venkatraman Ramakrishnan Texas Instruments, India T3: Design Automation and CAD Tools
Sachin Sapatnekar University of Minnesota T3: Design Automation and CAD Tools
Nikhil Tripathi Mentor Graphics (Calypto System Division), India T3: Design Automation and CAD Tools
Hao Zheng University of South Florida, United States T3: Design Automation and CAD Tools
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