VLSID & ES 2018 – Main Conference Technical Program – Detailed

Day 1 – 8th January 2018
Start End Track A Track B Track C Track S(Student) & Industry Forum User Design Track
7:30 AM 9:00 AM Registrations
9:00 AM 9:40 AM Ganesh Vandana and Welcome talks
9:45 AM 10:30 AM Keynote by Seagate
10:35 AM 11:20 AM Keynote by Qualcomm
11:25 AM 11:40 AM Inauguration of Exhibits
11:40 AM 11:55 AM Break Out
11:55 AM 1:15 PM Track 1A: Analog/RF – I Track 1B: Power Management Track 1C: FPGA – I Track 1F
11:55 AM 12:15 PM Track 1A.1
A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs
Uma Kulkarni, Chetan Parikh and Subhajit Sen
Indian Institute of Technology, Bombay
Track 1B.1
Rescheduling of Power Gating instructions for reduction of In-rush current
Sumanta Pyne
National Institute of Technology, Rourkela
Track 1C.1
Fault-tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs
Anju Johnson, Junxiu Liu, Alan Millard, Shvan Karim, Andy Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid and David Halliday
University of York, Ulster University
12:15 PM 12:35 PM Track 1A.2
Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplifier
Diego James, Abishek T. Kunnath, A. Purushothaman and Bibhu Datta Sahoo Amrita Vishwa Vidyapeetham University,
University of Illinois at Urbana-Champaign
Track 1B.2
Dynamic Thermal Management by using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors
Alankar V Umdekar, Arijit Nath, Shirshendu Das and Hemangee Kapoor
Indian Institute of Technology, Guwahati
Track 1C.2
FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications
Ravi Krishnan Unni, Vijayanand P and Dilip Y
Aeronautical Development Establishment, DRDO
12:35 PM 12:55 PM Track 1A.3
Feedback Biasing based Adjustable Gain Ultrasound Preamplifier for CMUTs in 45nm CMOS
Linga Reddy Cenkeramaddi
University of Agder
Track 1B.3
Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components
Sudipa Mandal, Aritra Hazra, Pallab Dasgupta and Rama Mohan Chunduri
Indian Institute of Technology, Kharagpur, Intel Technology India Pvt. Ltd
Track 1C.3
Image Compression using 2D-Discrete Wavelet Transform on a Light-Weight Reconfigurable Hardware
Nupur Jain, Mansi Singh and Biswajit Mishra
Dhirubhai Ambani Institute of Information and Communication Technology,Gandhinagar
12:55 PM 1:15 PM Track 1A.4
An Ultra Low Power, 10-bit Two-Step Flash ADC for Signal Processing Applications
Mahi Kittu, Amit Kapoor and Srinivas M.B
Birla Institute of Technology and Science, Hyderabad
Track 1B.4
DPFair Scheduling with Slowdown and Suspension
Sanjay Moulik, Arnab Sarkar and Hemangee Kapoor
Indian Institute of Technology, Guwahati
Track 1C.4
YaNoC: Yet another Network-on-Chip Simulation Acceleration Engine using FPGAs
Prabhu Prasad B M, Khyamling Parane and Basavaraj Talawar

National Institute of Technology, Surathkal
1:15 PM 2:15 PM Lunch
2:15 PM 2:55 PM Keynote Speech by Joerg Henkel “Embedded Systems”
3:05 PM 4:05 PM Panel Discussions (Automotive) by Mr. Chandak
4:05 PM 4:25 PM Networking Break and High Tea
4:25 PM 5:45 PM Track 2A: Security – I Track 2B: Test Track 2C: Devices and Emerging Technologies Track 1S
4:25 PM 4:45 PM Track 2A.1
An Energy-Efficient Trusted FSM Design Technique to Thwart Fault Injection and Trojan Attacks
Vijaypal Singh Rathor, Bharat Garg and G K Sharma
ABV-Indian Institute of Information Technology and Management, Gwalior
Track 2B.1
Towards Single Pin Scan for Extremely Low Pin Count Test
Mudasir Kawoosa, Rajesh Mittal, Maheedhar Jalasuthram and Rubin Parekhji
Texas Instruments India
Track 2C.1
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips
Oliver Keszocze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty and Rolf Drechsler
University of Bremen, Duke University, Johannes Kepler University
4:45 PM 5:05 PM Track 2A.2
Novel Variability Aware Path Selection for Self-Referencing Based Hardware Trojan Detection
Ramakrishna Vaikuntapu, Lava Bhargava and Vineet Sahula Malaviya

National Institute of Technology
Track 2B.2
Test-Time Reduction for Power-Aware 3D-SoC
Sabyasachee banerjee, Subhashis Majumder and Bhargab Bhattacharya
Heritage Institute of Technology, Kolkata, Indian Statistical Institute, Kolkata
Track 2C.2
Design Optimization at the Fluid-level Synthesis for Safe and Low-Cost Droplet-based Microfluidic Biochips
Arpan Chakraborty, Piyali Datta and Rajat Kumar Pal
University of Calcutta, Heritage Institute of Technology, Kolkata
5:05 PM 5:25 PM Track 2A.3
PPU: Privacy-Aware Purchasing Unit for Residential Customers in Smart Electric Grids
Amrita Roy Chowdhury and Parameswaran Ramanathan
University of Wisconsin-Madison
Track 2B.3
Identification of Faulty TSVs in 3D IC during Pre-bond Testing
Dilip Maity, Surajit Roy and Chandan Giri
Academy of Technology, Indian Institute of Engineering Science and Technology,Shibpur
Track 2C.3
Hysteresis Free sub-60 mV/dec Subthreshold Swing in Junctionless MOSFETs
Manish Gupta and Abhinav Kranti
Indian Institute of Technology, Indore
5:25 PM 5:45 PM Track 2A.4
Hardware Trojan Detection using ATPG and Model Checking
Jonathan Cruz, Farimah Farahmandi, Alif Ahmed and Prabhat Mishra
University of Florida
Track 2B.4
Modeling & Analysis of Redundancy based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache
Avishek Choudhury and Biplab Sikdar
New Alipore College, Kolkata, Indian Institute of Engineering Science and Technology,Shibpur
Track 2C.4
New Asymmetric Atomistic Model for the Analysis of Phase-engineered MoS2-Gold Top Contact
Richa Chakravarty, Dipankar Saha and Santanu Mahapatra
Indian Space Research Organization (ISRO), Indian Institute of Science, Bangalore
Day 2 – 9th January 2018
Start End Track A Track B Track C Track S(Student) & Industry Forum User Design Track
7:30 AM 8:00 AM Registrations
8:00 AM 8:30 AM Two Start-Up Presentations
8:30 AM 9:15 AM Keynote by Marvell
9:15 AM 10:00 AM Keynote by John Deere
10:00 AM 10:20 AM Break Out
10:20 AM 11:40 AM Track 3A: Security – II Track 3B: Oscillators Track 3C: FPGA – II Proposed Sponsored Tutorial
10:20 AM 10:40 AM Track 3A.1
Power Side Channel Resistance of RNS Secure Logic
Ravikumar Selvam and Akhilesh Tyagi
Iowa State University
Track 3B.1
A Novel Zero Blind Zone Phase Frequency Detector for Fast Acquisition in Phase Locked Loops
Sucheth S Kuncham, Manasa Gadiyar, Sushmitha Din K, Kiran Kumar Lad and Dr.Tonse Laxminidhi
National Institute of Technology, Surathkal
Track 3C.1
High Speed FPGA Fabric Aware CSD Recoding with Run-time Support for Fault Localization
Ayan Palchaudhuri and Anindya Sundar Dhar
Indian Institute of Technology, Kharagpur
10:40 AM 11:00 AM Track 3A.2
Positive Feedback Symmetric Adiabatic Logic against Differential Power Attack
Bhuvana B P and Kanchana Baashkaran V S
Vellore Insitute of Technology, Chennai
Track 3B.2
A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems
Manikandan RR, Vipul Singhal, Rajat Chauhan, Vinod Menezes and Mahesh Mehandale
Indian Institute of Science, Bangalore, Texas Instruments India Pvt. Ltd.
Track 3C.2
A Low-Power Accelerator for Action-Dependent Heuristic Dynamic Programming
Nan Zheng and Pinaki Mazumder
University of Michigan
11:00 AM 11:20 AM Track 3A.3
Online Detection and Reactive Countermeasure for leakage from BPU using TVLA
Sarani Bhattacharya, Shivam Bhasin and Debdeep Mukhopadhyay Nanyang Technological University, Singapore, Indian Institute of Technology, Kharagpur
Track 3B.3
A Quadrature-Phase Voltage Controlled Oscillator for Offset Phase and Frequency Compensation
Pragya Maheshwari, Pavan Kumar Sadhu, Mukesh Deharia, Nandakumar Nambath and Shalabh Gupta
Indian Institute of Technology, Bombay
Track 3C.3
Low Power Configurable Readout Integrated Circuit for Infrared Detector
Hari Shanker Gupta, Pranoy Datta, Maryam Shojaei Baghini, A S Kiran Kumar and Dinesh K Sharma
Indian Space Research Organisation (ISRO), Indian Institute of Technology, Bombay
11:20 AM 11:40 AM Track 3A.4
Secure Neural Circuits to Mitigate Correlation Power Analysis on SHA-3 Hash Function
Dhireesha Kudithipudi and James Thesing
Rochester Institute of Technology
Track 3B.4
CMOS Oscillator having stable frequency with process, temperature and voltage variation
Vikas Rana
STMicroelectronics Pvt Ltd
11:40 AM 11:50 PM Break Out
11:50 PM 1:10 PM Track 4A: Analog/RF – II Track 4B: Special Session Track 4C: Special Session Track 2F
11:50 AM 12:10 PM Track 4A.1
A 12.5Gbps Transmitter for Multi-Standard SERDES in 40nm Low Leakage CMOS
Biman Chattopadhyay, Sharath N Bhat, Gopalkrishna Nayak and Ravi Mehta
Silicon And Beyond Private Ltd.
Track 4B.1
Power Management Integrated Circuits
Session Organizer: Qadeer Khan, Indian Institute of Technology, Madras
Qadeer A. Khan, Indian Institute of Technology Madras
Seong-Joong Kim, University of Illinois at Urbana-Champaign
Punith R. Surkanti, Nokia, Inc.
Paul M. Furth, New Mexico State University
Track 4C.1
Design of Energy Efficient and Reliable VLSI Systems
Session Organizer: Jana Doppa, Washington State University
Sudeep Pasricha, Colorado State University
Jana Doppa, Washington State University
Partha Pratim Pande, Washington State University
Krishnendu Chakrabarty, Duke University
12:10 PM 12:30 PM Track 4A.2
A High efficiency body injected differential power amplifier at 2.4GHz for low power applications
Naga Sasikanth Mannem and Tarun Kanti Bhattacharyya
Indian Institute of Technology, Kharagpur
12:30 PM 12:50 PM Track 4A.3
A Novel Low Power Gm-C Continuous-Time Analog Filter With Wide Tuning Range
Palle Sundar Veerendranath, Vasantha M.H and Edoardo Bonizzoni
National Institute of Technology, Goa, University of Pavia, Italy
12:50 PM 1:10 PM Track 4A.4
0.36 nJ/bit MedRadio Band OOK Transmitter for Wearable Healthcare Applications
Abhishek Srivastava and Maryam Baghini,
Indian Institute of Technology, Bombay
1:10 PM 2:10 PM Lunch
2:10 PM 2:55 PM Keynote by Krish Chakraborthy “Lab on a Chip”
3:00 PM 3:45 PM Panel Discussions under WIE initiative
3:50 PM 4:35 PM Keynote #10 (Organized by Women In Engineering)
4:35 PM 4:55 PM High Tea
4:55 PM 6:15 PM Track 5A: Reliability and SRAMs Track 5B: VLSI Architecture Track 5C: Design Automation Track 2S
4:55 PM 5:15 PM Track 5A.1
Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique
Sai Aparna Aketi, Joycee Mekie and Hemal Shah
Indian Institute of Technology, Gandhinagar
Track 5B.1
An Efficient VLSI Architecture for Convolution Based DWT Using MAC
Noor Mahammad Sk and Mohamed Asan Basiri M Indian Institute of Information Technology Design and Manufacturing (IIITDM)
Kancheepuram, Indian Institute of Technology, Kanpur
Track 5C.1
Design space exploration of an execution-driven functional-simulation methodology
Ipsita Biswas Mahapatra, S K Nandy, Utkarsh Agarwal and Chandrashekhar Azad Indian Institute of Science, Indraprastha Institute of Information Technology, Bhagalpur
College of Engineering
5:15 PM 5:35 PM Track 5A.2
Impact of Device Aging on Early Mode Failures in Pulsed Latches
Ankur Shukla, Rahul Rao and James Warnock IBM India Private Ltd
Track 5B.2
Hardware-Efficient & Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network
Mahesh Murty and Rahul Shrestha
Indian Institute of Technology, Hyderabad, Indian Institute of Technology, Mandi
Track 5C.2
A Practical Methodology to Compress Technology Libraries using Recursive Polynomial Representation
International Institute of Information Technology, Hyderabad
Sneh Saurabh and Priyanka Mittal
5:35 PM 5:55 PM Track 5A.3
A 0.6V Retention Vmin Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology using Adaptive Source Bias
Ashish Kumar and Gangaikondan Visweswaran STMicroelectronics Pvt Ltd, PES University, Bengaluru, India
Track 5B.3
Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter
Mohd Tasleem Khan and Rafi Ahamed
Indian Institute of Technology, Guwahati
Track 5C.3
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems
Arindam Sinha Ray, Pranab Roy and Hafizur Rahaman
Indian Institute of Engineering Science and Technology, Shibpur
5:55 PM 6:15 PM Track 5A.4
A 7-nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance
M Sultan M Siddiqui, Sumit Srivastava, Dattatray Ramrao Wanjul, Manan Kumar Suthar and Sudhir Kumar
Synopsys India Pvt. Limited
Track 5B.4
Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system
Preyesh Dalmia, Vikas Choudhary, Abhinav Parashar, Akshi Tomar and Neeta Pandey
Delhi Technological University
Track 5C.4
Computing Fréchet Distance Metric based L-Shape Tile Decomposition for E-Beam Lithography
Siva Satyendra Sahoo, Bharadwaj Veeravalli and Akash Kumar
National University of Singapore, Technische Universitaet Dresden
6:15 PM 6:45 PM Networking Break
6:45 PM 8:05 PM Award Function & Cultural Program
8:05 PM 9:05 PM Banquet Dinner
Day 3 – 10th January 2018
Start End Track A Track B Track C Track S(Student) & Industry Forum User Design Track
7:30 AM 8:00 AM Registrations
8:00 AM 8:30 AM Two Start-Up Presentations
8:30 AM 9:15 AM Keynote #7 (Gold Sponsor)
9:20 AM 10:05 AM Keynote #8 (Invited)
10:05 AM 10:25 AM Break Out
10:25 AM 11:45 AM Track 6A: Analog/RF – II Track 6B: Regulators Track 6C: Embedded Systems – I Track 3S
10:25 AM 10:45 AM Track 6A.1
Sallen Key Switched Capacitor LPF with N-type Transistors
Kamal Kumar Chapagai and Pydi Ganga Bahubalindruni
Indraprasth Institute of Information Technology, Delhi
Track 6B.1
An NMOS Low Drop-out Voltage Regulator with -17dB Wide-band Power Supply Rejection for SerDes in 22FDX
Nitin Bansal and Rahul Gupta
Invecas Technolgies Pvt Ltd
Track 6C.1
Accelerating Hash Computations through Efficient Instruction-set Customisation
Mayuran Sivanesan, Anupam Chattopadhyay and Ronak Bajaj Nanyang Technological University, Singapore
10:45 AM 11:05 AM Track 6A.2
Pseudo-continuous Output Switched-Capacitor Amplifier for Rail-to-Rail Current Sensing Application
Anjali Gopinath, Ravi Kumar Adusumalli, Rohit Ranganathan and Arya S AMS Semiconductors India Pvt.Ltd
Track 6B.2
Single Inductor Dual Output Buck Converter for Low Power Applications and its Stability Analysis
Sowmya Sankaranarayanan, Chaitali Kulkarni, Aswanth Sreekumar, Laxminidhi Tonse, Rajat Chauhan and Vipul Singhal
National Institute of Technology, Surathkal, Texas Instruments India Pvt. Ltd.
Track 6C.2
Lightweight Forth Programmable NoCs
Vinay B. Y. Kumar, Deval Shah, Mandar Datar and Sachin Patkar Indian Institute of Technology, Bombay
11:05 AM 11:25 AM Track 6A.3
Design Considerations of a Sub-50 μW Receiver Front-end for Implantable Devices in MedRadio Band
Gregory Chang, Shovan Maity, Baibhab Chatterjee and Shreyas Sen Purdue University
Track 6B.3
A 0.29ps FOM Fast Transient Any Cap Stable LVR in 28FDSOI
PNitin Bansal, Saurabh Singh, Hemant Shukla and Madhvi Sharma
Invecas Technolgies Pvt Ltd, Cirrus Logic, STMicroelectronics Pvt Ltd
Track 6C.3
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs
John Jose and Abhijit Das Indian Institute of Technology, Guwahati
11:25 AM 11:45 AM Track 6A.4
A 0.6mW 1.6 dB Noise Figure Inductorless Shunt Feedback Wideband LNA With Gm Enhancement and Current Reuse in 65 nm CMOS
Narendra Nath Ghosh, Prakash Kumar Lenka, SriHarsa Vardan G and Ashudeb Dutta Indian Institute of Technology, Hyderabad
Track 6B.4
A High Performance Gated Voltage Level Translator with Integrated Multiplexer
Dharshak B S and Rahul Rao
IBM India Private Ltd
Track 6C.4
Towards Near Data Processing of Convolutional Neural Networks
Palash Das, Shivam Lakhotia, Prabodh Shetty and Hemangee k. Kapoor Indian Institute of Technology, Guwahati
11:45 AM 12:45 PM Lunch
12:45 PM 1:30 PM Keynote #9(Invited)
1:35 PM 2:20 PM Panel Discussions
2:25 PM 2:45 PM High Tea
2:45 PM 4:05 PM Track 7A: Security – III Track 7B: Verification and Validation Track 7C: Memory Track 4S
2:45 PM 3:05 PM Track 7A.1
A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things
Ujjwal Guin, Adit Singh, Mahabubul Alam, Janice Canedo and Anthony Skjellum
Auburn University
Track 7B.1
AMS-Miner: Mining AMS Assertions using Interval Arithmetic
Antonio Bruto da Costa, Shriya Dharade, Sudipa Mandal and Pallab Dasgupta
Institute of Technology, Kharagpur
Track 7C.1
Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory
Md Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin and Abhinav Kranti
Indian Institute of Technology, Indore, National Sun Yat-Sen University
3:05 PM 3:25 PM Track 7A.2
A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher
Jai Gopal Pandey, Tarun Goel and Abhijit Karmakar
Central Electronics Engineering Research Institute, Rajasthan
Track 7B.2
ELURA: A Methodology for Post-silicon Gate-level Error Localization Using Regression Analysis
Ankit Jindal, Binod Kumar, Kanad Basu and Masahiro Fujita
Institute of Technology, Bombay, Synopsys India Pvt. Limited, University of Japan
Track 7C.2
Energy-Efficient Dynamic Data Encoding for Multi-Level STT-MRAM
Mohammad Alfailakawi, Imtiaz Ahmad and Sarah Elghandour
Kuwait University
3:25 PM 3:45 PM Track 7A.3
Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study
Vishal Dey, Vikramkumar Pudi, Yuval Elovici and Anupam Chattopadhyay
Indian Institute of Engineering Science and Technology, Nanyang Technological
University, Singapore, Gurion University of the Negev, Israel
Track 7B.3
Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation
Xiaobang Liu and Ranga Vemuri
University of Cincinnati
Track 7C.3
Switching-Time Dependent PUF Using STT-MRAM
Ashwani Kumar, Shubham Sahay and Manan Suri,
Indian Institute of Technology, Delhi
3:45 PM 4:05 PM Track 7C.4
Floating Point Multiplication Mapping on ReRAM based In-Memory Computing Architecture
Tarun Vatwani, Arko Dutt, Debjyoti Bhattacharjee and Anupam Chattopadhyay,
Nanyang Technological University, Singapore
4:05 PM 4:35 PM Tea & Certificate Distribution
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