Tutorial Program

Start End Track 1 Track 2 Track 3 Track 4
        Day T1 – 6th January 2018

8:00 AM

9:00 AM

Tutorial Registration

9:00 AM
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1:00 PM

12:00 PM
&
5:00 PM

T1A: Embedded Systems

Assistive Technology for Visually Impaired: Embedded & Vision Solutions

M Balakrishnan (IIT Delhi) and

Chetan Arora (IIIT Delhi)

Full-day Tutorial

T1B: FinFETs and Beyond

Emerging Computational Devices, Architectures and Computational Models

Vijaykrishnan Narayanan (Penn State University, University Park, PA),

Arijit Raychowdhury (Georgia Institute of Technology, Atlanta, GA) and

Sumeet Kumar Gupta (Pennsylvania State University/Purdue University)

Full-day Tutorial

T1C: Analog and Mixed Signal

High-Speed Serial Links: Architectures and Circuits for Clock and Data Recovery (CDR)

Saurabh Saxena (IIT Madras) and

Nagendra Krishnapura (IIT Madras)

Full day Tutorial


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        Day T2 – 7th January 2018

8:00 AM

9:00 AM

Tutorial Registration

9:00 AM
&
1:00 PM

12:00 PM
&
5:00 PM

T2A: Safe Autonomous Systems

Safe Autonomous Systems: Real-Time Error Detection and Correction in Safety-Critical Signal Processing and Control Algorithms

Jacob Abraham (University of Texas, Austin, TX) and

Abhijit Chatterjee (Georgia Institute of Technology, Atlanta, GA)

Half-day Tutorial

T2B: Security and Verification

Hardware Intellectual Property (IP) Security and Trust: Challenges and Solutions

Prabhat Mishra (University of Florida, Gainesville, Florida, USA) and

Rajat Subhra Chakraborty, (IIT Kharagpur)

Half-day Tutorial

T2C: Emerging Technologies

Beyond von-Neumann Computing: Devices, Circuits, and Applications

Kaushik Roy (Purdue University, West Lafayette, IN)

Half-day Tutorial

T2G: Secure SSD Controllers for Cloud

Designing Reliable and Secure SSD Controllers For Cloud Storage

Erich F. Haratsch, Seagate Technology, Milpitas, CA, USA

Half-day Tutorial


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T2D: IoT Security

Privacy Assurances in the Internet of Things (IoT) World

Parameswaran Ramanathan (University of Wisconsin, Madison, WI)

Half-day Tutorial

T2E: IC Verification & Validation

Pre-Silicon Verification and Post-Silicon Validation: Dramatic Improvements through Disruptive Innovations

Subhasish Mitra (Stanford University, Stanford, CA), Srinivas Shashank Nuthakki (Stanford University, Stanford, CA), Eshan Singh (Stanford University, Stanford, CA)

Half-day Tutorial

T2F: Silicon Photonics

Silicon Nanophotonics for Future Manycore Chips: Opportunities and Challenges

Sudeep Pasricha (Colorado State University, Fort Collins, CO)

Half-day Tutorial

T2H: Automotive Battery Management Solutions

Automotive Battery Management Solutions

Philippe Perruchoud, NXP

Half-day Tutorial


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T1A : Embedded Systems

Assistive Technology for Visually Impaired: Embedded & Vision Solutions

M Balakrishnan (IIT Delhi) & Chetan Arora (IIIT Delhi)

Full-day Tutorial :

Abstract :- Census 2011 classifies more that 5 million people as visually disabled In India. AssisTech (Assistive Technology) group at IIT Delhi aims to develop technological solutions to address their two key challenges; namely independent mobility and access to education. In this tutorial, we will firstly brief about the challenge of mobility and education for visually impaired people. Solutions addressing these challenges could be developed using embedded sensors or with embedded computer vision. Our existing products like SmartCaneTM and OnBoard are embedded system based solutions and are aimed towards facilitating independent mobility. There have been major advances in vision based techniques including possibility of their implementation on low cost embedded platforms. This has encouraged us to visualize a device named MAVI (Mobility Assistant for Visually Impaired). Objective of MAVI is to create a platform that would be able to provide mobility assistance to a visually impaired person in an unstructured infrastructure of developing countries like India. In this tutorial we will discuss specific challenges and various vision techniques used in MAVI to address the requirements of safety, navigation and social inclusion. Designing a complex system like MAVI presents the designer with numerous choices of algorithms as well as platform/hardware resources. We will discuss the challenges in handling system level design complexities and explain our approach towards design space exploration for such systems. Further, we also observe that existing metrics employed in the literature to assess various vision algorithms are inadequate when it comes to complex systems like MAVI. We also propose the need for system level metrics. Finally, we will demonstrate apart from a MAVI prototype, other devices and solutions developed by the AssisTech group (http://assistech.iitd.ac.in/).

Speaker Bios :

M. Balakrishnan is a Professor in the Department of Computer Science & Engineering and currently Deputy Director(Strategy & Planning) at IIT Delhi. He obtained his B.E.(Hons.) in Electronics & Electrical Engg. from BITS Pilani in 1977 and Ph.D. from EE Dept. IIT Delhi in 1985. He worked as a Scientist in CARE, IIT Delhi from 1977 to 1985 where he was involved in designing and implementing real-time DSP systems. For the last 29 years, he is involved in teaching and research in the areas of digital systems design, electronic design automation and embedded systems. He has supervised 14 Ph.D. students, 3 MSR students, 173 M.Tech/B.Tech projects and published nearly 112 conference and journal papers. Further, he has held visiting positions in universities in Canada, USA and Germany. At IIT Delhi, he has been the Philips Chair Professor, Head of the Department of Computer Science & Engineering, Dean of Post Graduate Studies & Research and Deputy Director (Faculty). He has been associated with a number of initiatives to promote research at IIT Delhi. Along with seven graduating students and four other faculty colleagues he founded KritiKal Solutions in 2002. This was the first student-faculty led start-up in the Technology Business Incubation Unit at IIT Delhi.

ASSISTECH, a laboratory and research group co-founded by him, is involved in developing a number of assistive devices targeted towards mobility and education of the visually impaired. He has been a recipient of two National awards for his work in the disability space. SmartCaneTM is a mobility aid for visually impaired developed by his group and currently it is used by thousands of users in India and other countries.

Chetan Arora received Ph.D. in Computer Science and B.Tech in Electrical Engineering, both from IIT Delhi in 2012 and 1999 respectively. He did his Post Doctoral Research with Prof. Shmuel Peleg from 2012-2014 in Hebrew University, Israel. Since 2014, he is teaching as an Assistant Professor in Computer Science Department at IIIT Delhi. Chetan has published more than 20 papers in top computer vision journals and peer reviewed conferences. Prior to returning to academics, Chetan has spent over 10 years in industry, where he co-founded 3 startups, along with his counterparts in Japan and Israel, all working on computer vision products coming out of latest research ideas. Chetan has served as an area chair at ICVGIP 2016 and program co-chair for NCVPRIPG 2017. He has been actively involved in the area of computer vision for persons with disabilities and has organized multiple workshops to promote the same including Workshop on Assistive Vision held with ACCV 2016.


T1B : FinFETs and Beyond

Emerging Computational Devices, Architectures and Computational Models

Vijaykrishnan Narayanan (Penn State University, University Park, PA)
&
Arijit Raychowdhury (Georgia Institute of Technology, Atlanta, GA)
&
Sumeet Kumar Gupta (Pennsylvania State University/Purdue University)

Full-day Tutorial :

Abstract :- As traditional CMOS scaling nears the end of physical scaling, the need for new computational devices, models and architectures has become imperative. At the application level, the systems are evolving from number-crunching compute modules to intelligent systems capable of cognitive thinking. This course will look at the synergies that are required across the stack from new devices to new computational models for designing future computing systems. This course will enable attendees to understand the inter-twined nature of design optimization that requires one to interact with experts in different domains. The students will be exposed to simulation tools and modelling techniques to help explore new circuits and architectures. As physical dimensional scaling alone has ceased to be the key factor driving the industry, many innovations have occurred in designing new types of logic switches including changes to their structure (such as three-dimensional FinFETs), their underlying physics (use of tunneling for steep-switching devices), the material systems (integration of ferro-electrics in gate stack for Negative Capacitance FETs). The first part of the lecture will introduce these devices, simulation models and accompanying circuit innovations. There has been a world of revolution in the memory devices with the emergence of many non-volatile memory technologies and their tight integration in cross-point architectures. These memory systems have enabled new styles of computing systems such as the non-volatile processor for internet of thing systems and neuromorphic computing systems for cognitive computing. The lectures will focus on the synergistic coordination in advances in devices to system design. Neuromorphic systems also leverage new advances in technology such as cross-point memory arrays to integrate computing and store. Another emerging novel computational model is based on the principle “let physics do the computation”. This technique focuses on using the intrinsic operation mechanism of devices (such as nanoscale electronic coupled oscillators) to do the computation, instead of building complex circuits with standard transistors to carry out the same function. The primary objective is to train the next generation researchers and practitioners that can understand the synergy across the stack from devices to applications. This will prepare the next generation workforce for the beyond Moore era using post-CMOS devices and new computational paradigms beyond Von-Neumann computing models. This course will introduce the following topics: [1] Emerging logic and memory devices: What value do they add for circuit designers/architects? [2] Circuit/Architecture design using Emerging Logic and Memory devices [3] Neuromorphic and Brain-Inspired Computing using emerging devices [4] Computing Using Coupled Dynamical Systems.

Speaker Bios :

Vijaykrishnan Narayanan is a Distinguished Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. He has more than 400-refereed publications and has 17000+ citations to his work with an h-index of 68. He is a Fellow of IEEE and Association of Computing Machinery. He is the Editor-in-Chief of IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems and served as the founding Co-editor-in-chief of ACM Journal of Emerging Technologies in Computing Systems. He is the chair of ACM Special Interest Group on Design Automation. He has won several awards in recognition of his research including the IEEE Micro Top Picks for 2016, ASPDAC ten-year retrospective most influential paper award, IEEE Transactions on VLSI Best Paper Award, One of the most significant papers of FPL in the 25-year history of Conference. He is listed in the Hall of Fame of the top computer architecture conferences: ISCA and HPCA. He also owns multiple patents on architectures for emerging technologies and applications. He has provided invited technical briefing at the US Senate and invited demonstration at the Science Fair at the US Congress. He has also been an invited attendee at the White House Brain Conference. His work has been widely featured in technical press. Prof. Narayanan leads an internationally renowned National Science Foundations (NSF) expeditions-in-computing center and is an investigator of three other major multi-university centers: DARPA/SRC LEAST Center, NSF ERC ASSIST and NSF/SRC E2CDA centers.

Arijit Raychowdhury is currently an Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology where he currently holds the ON Semiconductor Junior Research Professorship. He received his Ph.D. degree in Electrical and Computer Engineering from Purdue University. He joined Georgia Tech in January, 2013. His industry experience includes five years as a Staff Scientist in the Circuits Research Lab, Intel Corporation and a year as an Analog Circuit Designer with Texas Instruments Inc. His research interests include digital and mixed-signal circuit design, design of on-chip sensors, memory, and device-circuit interactions. Dr. Raychowdhury holds more than 25 U.S. and international patents and has published over 150 articles in journals and refereed conferences. He is the winner of the NSF CRII Award, 2015; Intel Labs Technical Contribution Award, 2011; Dimitris N. Chorafas Award for outstanding doctoral research, 2007; the Best Thesis Award, College of Engineering, Purdue University, 2007; Best Paper Awards at the International Symposium on Low Power Electronic Design (ISLPED) 2012, 2006; IEEE Nanotechnology Conference, 2003; SRC Technical Excellence Award, 2005; Intel Foundation Fellowship 2006, NASA INAC Fellowship 2004, and the Meissner Fellowship 2002. Dr. Raychowdhury is a Senior Member of the IEEE.

Sumeet Kumar Gupta received the B. Tech. degree in Electrical Engineering from the Indian Institute of Technology, Delhi, India in 2006, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Purdue University, West Lafayette IN in 2008 and 2012, respectively. Dr. Gupta is currently an Assistant Professor of Electrical Engineering at The Pennsylvania State University. Previously, he was a Senior Engineer at Qualcomm Inc. in San Diego CA, where he developed circuit design techniques and benchmarking methodologies of standard cells in deeply scaled technologies. He has also worked as an intern at National Semiconductor, Advanced Micro Devices Inc. and Intel Corporation in 2005, 2007 and 2010, respectively. His research interests include nano-electronics and spintronics, device-circuit-architecture co-design in post-CMOS technologies, low power variation aware VLSI circuit design and nano-scale device-circuit modeling and simulations. He has published over 70 articles in refereed journals and conferences and is a member of IEEE. Dr. Gupta was the recipient of 2016 DARPA Young Faculty Award, an Early Career Professorship by Penn State in 2014, the 6th TSMC Outstanding Student Research Bronze Award in 2012 and Intel Ph.D. Fellowship in 2009. He has also received Magoon Award from the School of Electrical and Computer Engineering, Purdue University, and the Outstanding Teaching Assistant Award from the Teaching Academy and the Office of the Provost, Purdue University, both in 2007. He was awarded a certificate of recognition for outstanding job during the summer internship by Intel Labs and certificates of merit for excellent academic performance at IIT Delhi.


T1C : Analog and Mixed Signal

High-Speed Serial Links: Architectures and Circuits for Clock and Data Recovery (CDR)

Saurabh Saxena (IIT Madras) & Nagendra Krishnapura (IIT Madras)

Full-day Tutorial :

Abstract :- Serial links behave as arteries of computing systems while transferring data from one point to the other and clock and data recovery (CDR) block has the responsibility of recovering the bits error-free at the other end of transmission. This tutorial will present the basic requirements of CDRs and relate their performance metrics to different architectures and loop components with tradeoffs for different implementations. Particularly, this tutorial will compare different CDR architectures: linear vs. bang-bang, full-rate vs. sub-rate architectures, analog vs. digital vs. hybrid loops, oscillator vs. phase interpolator vs. embedded phase-locked loops (PLLs), reference-less vs. reference-based CDRs, and CMOS vs. CML vs. charge-based receiver front-end of CDRs.

Introduction and basic architectures of CDRs: We will start with introduction to serial links and motivation for learning CDR in the serial data communication. While identifying the basic requirements of a CDR, we will discuss its performance metrics like jitter tolerance (JTOL), jitter transfer function (JTRAN), and jitter generation (JGEN) and consequences of specific demands on CDR’s architecture and design. We will discuss, analyze, and compare basic design of fullrate/sub-rate CDRs with their analog, digital, and hybrid implementations. Realization of CDR’s front-end with CMOS, CML, and charge-based circuits will also be studied.

CDRs for multi-lane chip-to-chip links: We will discuss tradeoffs between power/area and performance for CDR’s basic architectures in a multi-lane chip-to-chip application. Addressing the problems with conventional architectures, we will compare the following: wide-range ring oscillator based CDR vs. narrow-range LC oscillator based CDR, feedback loop with oscillator vs. phase interpolator or phase rotator based frequency/phase tracking in the feedback loop, and ring/LC oscillator vs. embedded phase-locked loop as a digitally controlled oscillator (DCO). We will examine circuit-level design of building blocks like phase interpolator, phase rotator, and PLL for CDRs.

CDRs for repeaters in long-haul communication: CDRs in repeaters require a wide JTOL bandwidth and low JTRAN bandwidth and traditional type-II architectures experience a direct tradeoff between JTOL and JTRAN bandwidth. So, we will examine architectures with decoupled JTOL and JTRAN bandwidth and discuss such architectures employing phase-rotating PLL (PRPLL), or phase interpolator, or delay lines.

Frequency detectors: Frequency detection of a random bit sequence is a critical part of CDR. Traditionally, a prior knowledge of data rate and a fixed reference for each receiver have been used for phase/frequency tracking of the incoming data. Since, an access to the data rate and a reference clock for each CDR is costlier, we will examine a couple of frequency detection techniques and their implementation without prior information or reference clock for the received data.

Speaker Bios :

Nagendra Krishnapura obtained his B.Tech. from the Indian Institute of Technology, Madras, India and his Ph.D. from Columbia University, New York. He has worked as an analog design engineer at Celight Inc., Multilink, and Vitesse semiconductor. He has taught analog circuit design courses at Columbia University as an adjunct faculty. He is currently an associate professor at the Indian Institute of Technology Madras. His interests are analog and RF circuit design and analog signal processing. He has been an associate editor of the IEEE Transactions on Circuits and Systems II: Express Briefs and is currently an associate editor of the IEEE Transactions on Circuits and Systems I: Regular Papers.

Saurabh Saxena (S’10-M’16) received the B.Tech. degree in electrical engineering, the M.Tech. degree in microelectronics and VLSI design from the Indian Institute of Technology Madras, Chennai, India, in 2009, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, IL, USA in 2015. He is currently an Assistant Professor in the Department of Electrical Engineering at Indian Institute of Technology Madras, Chennai, India. He serves as a reviewer for the IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE Transactions on Very Large Scale Integration Systems, and IEEE International Symposium on Circuits and Systems. His research interests include delta-sigma modulators, high speed I/O interfaces, and clocking circuits.


T2A : Safe Autonomous Systems

Safe Autonomous Systems: Real-Time Error Detection and Correction in Safety-Critical Signal Processing and Control Algorithms

Jacob Abraham (University of Texas, Austin, TX)
&
Abhijit Chatterjee (Georgia Institute of Technology, Atlanta, GA)

Half-day Tutorial :

Abstract :- While the last two decades have seen revolutions in computing and communications systems, the next few decades will see a revolution in the use of every-day robotics and artificial intelligence in broad societal applications. Examples of such systems include sensor networks, the smart power grid, self-driven cars and autonomous drones. Such systems are driven by signal processing, control and learning algorithms that process sensor data, actuate control functions and learn about the environment in which these systems operate. The trustworthiness and safety of such systems is of paramount importance and has significant impact on the commercial viability of the underlying technology. As a consequence, anomalies in system operation due to computation errors in on-board processors, degradation and failure of embedded sensors, actuators and electro-mechanical subsystems and unforeseen changes in their operation environment need to detected with minimum latency. Such anomalies also need to be  mitigated in ways that ensure the safety of such systems under all possible failure scenarios. Many future systems will be self-learning in the field.  It is necessary to ensure that such learning does not compromise the safety of all human personnel involved in the operation of such systems.

To enable safe operation of such systems, the underlying hardware needs to be tuned in the field to maximize performance, reliability and error-resilience while minimizing power consumption. To enable such dynamic adaptation, device operating conditions and the onset of soft errors are sensed using post-manufacture and real-time checking mechanisms. These mechanisms rely on the use of built-in sensors and/or low-overhead function encoding techniques to detect anomalies in system functions. A key capability is that of being able to deduce multiple performance parameters of the system-under-test using compact optimized stimulus using learning algorithms. The sensors and function encodings assess the loss in performance of the relevant systems due to workload uncertainties, manufacturing process imperfections, soft errors and hardware malfunction and failures induced by electro-mechanical degradation. These are then mitigated through the use of algorithm-through-circuit level compensation techniques based on pre-deployment simulation and post-deployment self-learning. These techniques continuously trade off performance vs. power of the individual software and hardware modules in such a way as to deliver the end-to-end desired application level Quality of Service (QoS), while minimizing energy/power consumption and maximizing reliability and safety. Applications to signal processing, and control algorithms for example autonomous systems will be discussed.

Speaker Bios :

Jacob A. Abraham is a Professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. He is also director of the Computer Engineering Research Center and holds a Cockrell Family Regents Chair in Engineering. He received the Bachelor’s degree in Electrical Engineering from the University of Kerala, India, in 1970. His M.S. degree, in Electrical Engineering, and Ph.D., in Electrical Engineering and Computer Science, were received from Stanford University, Stanford, California, in 1971 and 1974, respectively. From 1975 to 1988 he was on the faculty of the University of Illinois, Urbana, Illinois.

Professor Abraham’s research interests include VLSI design and test, formal verification, and fault-tolerant computing. He is the principal investigator of several contracts and grants in these areas, and a consultant to industry and government on testing and fault-tolerant computing. He has over 400 publications, and has been included in a list of the most cited researchers in the world. He has supervised more than 80 Ph.D. dissertations. He is particularly proud of the accomplishments of his students, many of whom occupy senior positions in academia and industry. He has served as associate editor of several IEEE Transactions, and as chair of the IEEE Computer Society Technical Committee on Fault-Tolerant Computing. He has been elected Fellow of the IEEE as well as Fellow of the ACM, and is the recipient of the 2005 IEEE Emanuel R. Piore Award.

Abhijit Chatterjee is a professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric’s key technical achievements in 1992 and was cited by the Wall Street Journal. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC).

Dr. Chatterjee has authored over 400 papers in refereed journals and meetings and has 20 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests include error-resilient signal processing and control systems, mixed-signal/RF/multi-GHz design and test and adaptive real-time systems.


T2B : Security and Verification

Hardware Intellectual Property (IP) Security and Trust: Challenges and Solutions

Prabhat Mishra (University of Florida, Gainesville, Florida, USA) & Rajat Subhra Chakraborty, (IIT Kharagpur)

Half-day Tutorial :

Abstract :- Reusable hardware intellectual property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design/verification cost while meeting aggressive time-tomarket constraints. Growing reliance on reusable, functionally pre-verified hardware IPs and wide array of CAD tools during SoC design – often gathered from untrusted 3rd party vendors – severely affects the security and trustworthiness of SoC computing platforms. Major security issues in the hardware IPs at different stages of SoC life cycle include piracy during IP evaluation, reverse engineering, cloning, counterfeiting, as well as malicious, hard-to-detect hardware modifications in the hardware IPs. The global electronic piracy market is growing rapidly and is now estimated to be over $1B/day [1], of which a significant part is related to hardware IPs. Due to evergrowing computing demands, modern SoCs tend to include many heterogeneous processing IP cores, together with reconfigurable cores e.g. embedded FPGA in order to incorporate logic that is likely to change as standards and requirements evolve. Such design practices greatly increase the number of untrusted components in the SoC design flow and make the overall system security a pressing concern. There is a critical need to analyze the SoC security issues and attack models due to involvement of multiple untrusted entities through the 3rd party IP (3-PIP) route – and develop low-cost effective countermeasures. These countermeasures would encompass hardware encryption and obfuscation, intelligent automatic test pattern generation (ATPG), hardware watermarking and fingerprinting, and certain analytic methods derived from the behavioral aspects of the hardware IPs to enable trusted operation with untrusted components.

In this tutorial, we plan to provide a comprehensive coverage of both fundamental concepts and recent advances in validation of security and trust of hardware IPs. It examines the state-of-the-art in research in this challenging area as well as industrial practice, and points to important gaps that need to be filled in order to develop a validation and debug flow to establish the necessary trust level of hardware IPs, eventually leading to secure SoC systems. The tutorial presenters with complementary areas of expertise and extensive experience of consulting for leading companies and R&D labs will provide a unique snapshot of the challenges, cutting-edge solutions and open problems in this area. The selection of topics covers a broad spectrum and will be of interest to a wide audience including design, validation, security, and debug engineers.

The proposed tutorial consists of four parts. The first part introduces security vulnerabilities and various challenges associated with trust validation for hardware IPs. Part II covers various demonstrated attacks and design modification based countermeasures such as hardware watermarking and obfuscation. Part III covers formal methods, simulation-based approaches as well as side channel analysis for security and trust validation in hardware IPs. Finally, Part V concludes this tutorial with discussion on emerging issues and future directions.

Speaker Bios :

Prabhat Mishra is a Professor in the Department of Computer and Information Science and Engineering at the University of Florida. His research interests include design automation of embedded systems, energy-aware computing, hardware security and trust, system validation and verification, reconfigurable architectures, and postsilicon debug. He received his Ph.D. in Computer Science and Engineering from the University of California, Irvine. He has published five books and more than 150 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award, IBM Faculty Award, three best paper awards, and EDAA Outstanding Dissertation Award. Prof. Mishra currently serves as the Deputy Editor-in-Chief of IET Computers & Digital Techniques, and as an Associate Editor of ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on VLSI Systems, and Journal of Electronic Testing. He has served on many conference organizing committees and technical program committees of premier ACM and IEEE conferences. He is currently serving as an ACM Distinguished Speaker. Prof. Mishra is an ACM Distinguished Scientist and a Senior Member of IEEE.

Rajat Subhra Chakraborty is currently an Associate Professor at CSE Department of IIT Kharagpur. He received his Ph.D. from Case Western Reserve University (U.S.A.) and B.E. from Jadavpur University. He has professional experience of working at National Semiconductor, Bangalore, India and Advanced Micro Devices (AMD), Santa Clara, USA. His research interests include Hardware Security, VLSI Design and Design Automation and Digital Content Protection. He holds 2 Granted U.S. patents, 2 edited volumes, and has co-authored 3 books, 7 book chapters, and over 75 publications in international journals and conferences. His work has received close to 2000 citations till date, and a paper co-authored by him won the Best Paper Award at the IWDW’16 workshop. He has been the Program Chair of SPACE’14, SPACE’15 and AHSA-DSD’17, and regularly features in the program committee of top international conferences. He has received several prestigious international and national awards such as IEI Young Engineers Award (2016), IBM Shared University Research (SUR) Award (2015), Royal Academy of Engineering (U.K.) RECI Fellowship (2014), IBM Faculty Award (2012). Dr. Chakraborty is a Senior Member of IEEE and a Senior Member of ACM.


T2C : Emerging Technologies

Beyond von-Neumann Computing: Devices, Circuits, and Applications

Kaushik Roy (Purdue University, West Lafayette, IN)

Half-day Tutorial :

Abstract :- Beyond von-Neumann Computing: Devices, Circuits, and Applications, Will be updated soon.

Speaker Bios :

Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 700 papers in refereed journals and conferences, holds 15 patents, supervised 75 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).

Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award (IEEE Charles Doeser award) , Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD Vannevar Bush Faculty Fellow Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay) and Global Foundries visiting Chair at National University of Singapore. He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings — Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.


T2D : IoT Security

Privacy Assurances in the Internet of Things (IoT) World

Parameswaran Ramanathan (University of Wisconsin, Madison, WI)

Half-day Tutorial :

Abstract :- Most Internet-of-Things (IoT) applications collect and aggregate data from a large number of sensors/users. The data often contains sensitive information related to the associated users and system. In recent years, there is extensive research on techniques to assure confidentiality of sensitive information in such systems. In this tutorial, we will introduce the privacy challenge, review the different approaches for privacy assurances in literature, and highlight open issues that need further investigation. The tutorial will use example from smart grids, smart homes, smart cities, mobile computing, and intelligent transportation systems to illustrate the solution approaches. This tutorial will be of interest to undergraduate and graduate students working in different IoT applications areas such as smart city projects, smart homes, and mobile computing. Industrial participants working in IoT technologies will also benefit from this tutorial. Lecturers in Indian engineering colleges who are teaching courses in security and privacy can also use this tutorial to not only get a broad overview but also to understand recent advances in the area. The tutorial will be self-contained.

Speaker Bios :

Parmesh Ramanathan received the B. Tech degree from the Indian Institute of Technology, Bombay, India, in 1984, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1986 and 1989, respectively. Since 1989, Dr. Ramanathan has been faculty member in the Department of Electrical and Computer Engineering, University of Wisconsin, Madison, where he is presently an Associate Dean for Graduate Education. He also served as a Chair of Department of Electrical and Computer Engineering from 2005-2009. He has served as consultant to AT&T Laboratories, Telcordia Technologies, and Hewlett Packard Laboratories. He was also a Visiting Professor at Kanwal Rekhi School of Information Technology, Indian Institute of Technology, Bombay, India in 2004 and Visiting Researcher at Microsoft Research in 2010. Dr. Ramanathan’s research interests include real-time systems, wireless and wireline networking, faulttolerant computing, and distributed systems. He has served as an Associate Editor for IEEE Transactions on Mobile Computing, Associate Editor for IEEE Transactions on Parallel and Distributed Computing (1996–1999) and Elsevier AdHoc Networks Journal (2002–2005). He was General Chair of Mobicom (2011) and MASS (2013). In 2009, he was elevated to Fellow of IEEE for his contributions to real-time systems and networks.


T2E : IC Verification & Validation

Pre-Silicon Verification and Post-Silicon Validation: Dramatic Improvements through Disruptive Innovations

Subhasish Mitra (Stanford University, Stanford, CA), Srinivas Shashank Nuthakki (Stanford University, Stanford, CA),
Eshan Singh (Stanford University, Stanford, CA)

Half-day Tutorial :

Abstract :- You have all spent weeks or months of onerous manual effort, from writing assertions to running long simulations (with limited success for corner-case bugs) or debugging false positives. This tutorial will give you a unique hands-on experience on how to detect and localize difficult bugs automatically, in just a few hours, during pre-silicon verification and post-silicon validation.

We present the Quick Error Detection (QED) technique for post-silicon validation and debug. QED drastically reduces error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as an observable failure. Symbolic QED combines QED principles with a formal engine for both pre- and post-silicon validation.

Results from several commercial designs demonstrate:

  1. For billion transistor-scale designs, you can now detect and localize difficult logic design bugs automatically (without having to write design-specific assertions) in only a few (~3) hours during pre-silicon verification.
  2. You can now drastically improve error detection latencies of post-silicon validation tests by up to 9 orders of magnitude for quick debug, from billions of clock cycles to very few clock cycles, and simultaneously improve bug coverage.
  3. You can now automatically localize bugs in billion transistor-scale designs during post-silicon debug, e.g., narrow locations of electrical bugs to a handful of flip-flops (~18 for a design with ~1million flip-flops), in only a few (~9) hours.

QED and Symbolic QED are effective for logic design bugs and electrical bugs inside processor cores, hardware accelerators, and uncore components such as cache controllers, memory controllers, interconnection networks or power management units. QED techniques have been successfully used in industry.

Speaker Bios :

Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation focus area of the Stanford SystemX Alliance. He is also a faculty member of the Stanford Neurosciences Institute. Prof. Mitra holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI in Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation.

Prof. Mitra’s research interests range broadly across robust computing, nanosystems, VLSI design, validation, test and electronic design automation, and neurosciences. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer and the first three-dimensional nanosystem with computation immersed in data storage. These demonstrations received wide-spread recognitions (cover of NATURE, Research Highlight to the United States Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post and numerous others worldwide). His earlier work on X-Compact test compression has been key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools.

Prof. Mitra’s honors include the ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation’s Technical Excellence Award, the Intel Achievement Award (Intel’s highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He and his students published several award-winning papers at major venues: ACM/IEEE Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors “for being important to them during their time at Stanford.”

Prof. Mitra served on the Defense Advanced Research Projects Agency’s (DARPA) Information Science and Technology Board as an invited member. He is a Fellow of the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE).

Eshan Singh received an ScB in Electrical Engineering, along with an AB in Economics, from Brown University in 2009. After completing an MS in Electrical Engineering from Stanford in 2011, Eshan spent three years at Intel as a Component Design Engineer. Eshan returned to Stanford in 2014 and is currently a PhD candidate in the Stanford Robust Systems Group with interests in VLSI design, 3-D integrated circuits, computer architecture, validation and debug. His current research focuses on addressing challenges in validation and debug, specifically aiming to improve bug localization, increase automation and reduce debug time.

Srinivasa Shashank Nuthakki is a PhD student working in Prof. Subhasish Mitra’s Robust Systems Group at Stanford University. He received the B.Tech. (Hons.) degree in Electronics and Electrical Communication Engineering and the M.Tech. degree in Microelectronics and VLSI Design from the Indian Institute of Technology, Kharagpur, in 2016. His current research interests include pre-siiicon verification, post-silicon validation, formal methods, hardware/software security and computer architecture.


T2F : Silicon Photonics

Silicon Nanophotonics for Future Manycore Chips: Opportunities and Challenges

Sudeep Pasricha (Colorado State University, Fort Collins, CO)

Half-day Tutorial :

Abstract :- The need for high performance and energy-efficient communication between processing cores has never been more critical. With levels of integration growing from tens of cores on a single chip today to hundreds of cores in emerging manycore chip architectures, there is immense pressure on the onchip communication fabric to support the many more quality of service (QoS) requirements and higher bandwidths for data transfers than ever before. An important consequence of this trend is that chip power and performance are now beginning to be dominated not by processor cores but by the components that facilitate transport of data between processors and memory. Unfortunately, traditional electrical wires that make up the backbone of communication fabrics of manycore chips today are facing unprecedented challenges in ultra-deep nanoscale CMOS fabrication technologies. These wires are becoming slower, more power hungry, and less reliable. We are thus at a critical juncture where the power, bandwidth, and latency costs of communication must scale favorably to meet the needs of manycore processing chips in the near future. A failure to adequately respond to this challenge will create a brick wall that will impede advances in all forms of computing.

Silicon nanophotonics has emerged in recent years as one of the most promising solutions to overcome the challenge of worsening communication performance with technology scaling. Recent breakthroughs in silicon nanophotonic device fabrication and CMOS integration have presented computer architects with an opportunity to explore both on-chip and chip-to-chip communications with optical networks that have significant advantages in bandwidth density, energy-efficiency, and propagation delay over traditional electrical solutions. Not surprisingly, the challenge of designing silicon nanophotonic communication fabrics is today actively being pursued by a number of researchers worldwide, and from a variety of different perspectives. New nanophotonic devices (e.g., modulators, photodetectors, waveguides) are emerging from academia and research labs, as are new nanophotonics based on-chip network architectures, and tools for rapid design and analysis. Many semiconductor companies (e.g., Intel, IBM) have begun investing heavily into silicon nanophotonics and are releasing functional prototypes. Silicon photonic foundries are also emerging to allow low-cost fabrication of nanophotonic components on silicon chips. However, silicon nanophotonic interconnects in manycore chips will not result in a one-for-one replacement of electrical interconnects. The lack of practical buffering and the fundamental circuit switched nature of optical data communications requires holistic and innovative approaches to designing system-wide photonic interconnection networks. New network devices, circuits, architectures, and protocols are required that incorporate the unique characteristics of the optical physical layer.

This tutorial aims to provide a comprehensive overview of silicon nanophotonics for future manycore chip architectures. The first part of the tutorial will educate the audience on the basics of silicon nanophotonics technology as well as the state-of-the-art in silicon nanophotonic fabrication and prototyping from industry and academia. Next, the challenges related to reliability, energy consumption, performance, and thermal stability of silicon photonics building blocks will be discussed. Subsequently, device-level, circuit-level, and architecture-level solutions will be comprehensively surveyed and presented, where the goal is to overcome the key challenges to the low cost integration of silicon nanophotonic interconnects at the chip-scale. Lastly, cross-layer solutions that combine techniques at the device, circuit, architecture, and/or system levels will be presented. Such solutions represent a very promising approach to achieving fault tolerance, energy efficiency, high performance, and thermal stability with much lower overheads than traditional single layer solutions. The tutorial will conclude with a discussion of open challenges and research problems in the area of silicon nanophotonics. The target audience for this tutorial is quite broad, from students of VLSI design who want to learn about this exciting area, to researchers and industry practitioners who want to get an updated view of recent developments in the area.

Speaker Bios :

Sudeep Pasricha received the B.E. in electronics and communication engineering from Delhi Institute of Technology, Delhi, India, in 2000, and his Ph.D. in computer science from the University of California, Irvine in 2008. Between 2000 and 2008 he also worked as a design engineer for several years at STMicroelectronics and Conexant. He joined Colorado State University (CSU) in 2008. He is currently a Monfort and Rockwell-Anderson Associate Professor in the Department of Electrical and Computer Engineering and the Department of Computer Science at CSU, where he is also the Chair of Computer Engineering and Director of the Embedded Systems and High Performance Computing (EPiC) Laboratory. Dr. Pasricha received the 2015 IEEE/TCSC Award for Excellence for a mid-career researcher, the 2014 George T. Abell Outstanding mid-career faculty award, and the 2013 AFOSR Young Investigator Award. His research on silicon photonics for 2D and 3D manycore computing has been recognized with three Best Paper Awards at the ACM SLIP 2016, ACM GLSVLSI 2015, and IEEE ISQED 2010 conferences, as well as a Best Paper Award Candidate selection at IEEE ISQED 2016. He is currently in the Editorial Board of ACM TECS, IEEE TCAD, IEEE TMSCS, IEEE D&T, IEEE CM, and JPDC. He is currently or has been an Organizing Committee Member of several IEEE/ACM conferences, including DAC, ESWEEK, GLSVLSI, NOCS, RTCSA, IGSC, VLSID, and ICESS.


T2G : Secure SSD Controllers for Cloud

Designing Reliable and Secure SSD Controllers For Cloud Storage

Erich F. Haratsch, Seagate Technology, Milpitas, CA, USA

Half-day Tutorial :

Abstract :- The data being generated world-wide has been growing exponentially and a significant portion of the data is stored in the cloud. Solid State Disks are now being widely used for cloud storage since they offer attractive capacities and performance characteristics. The capacity of SSDs has increased by the shift from planar to 3D NAND, and by the use of Triple-Level Cell technology. This tutorial will explain key concepts and architectures for the design of reliable and secure SSD controllers. SSD controllers need to implement host interfaces such SATA, SAS and PCI/NVMe. In addition, SSD controllers implement a flash translation layer that maps logical addresses from the host to physical addresses on the flash. Since 3D NAND flash wears out and the error rate increases with the number of program/erase cycles and read operations, SSD controllers need to implement complex error correction techniques and media management functions so that the reliability targets for cloud applications can be achieved. Also, SSD controllers need to implement the latest encryption standards to provide secure data storage. Compression algorithms help to improve the performance and lifetime of SSDs. This tutorial will illustrate the presented concepts based on actual measured results for state-of-the art SSDs.

Speaker Bios :

Erich F. Haratsch is Director of Engineering at Seagate Technology, where he is responsible for the architecture of flash controllers. He leads the development of hardware and firmware features that improve the performance, quality of service, endurance, error correction and media management capabilities of solid-state drives. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in more than one billion chips. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 40 peer-reviewed journal and conference papers, and holds more than 100 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).


T2H : Automotive Battery Management Solutions

Automotive Battery Management Solutions
Philippe Perruchoud, NXP


Half-day Tutorial :

Abstract :- Objects mobility and connectivity is one of the fastest growing markets stirred by the rise of innovative technologies coupled with continuously more stringent sustainability policies. Among those fast market changes, the automotive sector will be no exception with major evolution of disruptive technologies such as autonomous driving, electrification and connectivity. One of the pillar of the electrification transformation is the ability to store energy that is useable in electric form at a reasonable price, with acceptable availability and with extremely high safety for the end user. The Battery Management Systems (BMS) architecture is at the heart of this fast transformation and its design requires careful consideration in order to provide accurate available energy status, information of the battery health and its safety and to maximize battery lifetime and stored energy.

In this tutorial, you will review the basics of battery technologies and what are the critical parameters that require monitoring and the various solutions that are widely used. Then you will learn about the different architectures commonly used for various automotive applications ranging from 14V systems to 800V systems for full EVs. You will also learn about the market requirements in terms of functional safety and how it can be implemented at system level and its impact on the Analog Front End circuit which is that the heart of the BMS system. You will

Speaker Bios :

Philippe Perruchoud received the M.S. degree in Electrical Engineering from the National Institute of Applied Sciences (INSA), Toulouse, France in 1992. He joined Motorola Semiconductors application team focusing on power electronics for automotive and Automotive Electrification. He is now the manager of the application team supporting the BMS products family at NXP semiconductors. He owns several patents on driving techniques for power applications and wrote several papers in IEEE conferences.

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