Call for Papers

This joint conference is a forum for researchers and designers to present and discuss current topics in VLSI design, electronic design automation, embedded systems, and emerging technologies. Two days of tutorials (January 5-6) will be followed by three days (January 7-9) of regular paper sessions, special sessions, and embedded tutorials. The program will also include industry sessions along with exhibits, panel discussions, design contest, and Ph.D. forum.

TOPICS OF INTEREST: Regular papers are invited in all areas of VLSI design and embedded systems, including but not limited to the following categories:

Intelligence on Silicon: Smart autonomous systems, machine learning techniques, cognitive systems, artificial intelligence, machine learning for VLSI CAD, data analytics, neuromorphic and brain-inspired computing, analysis of data from VLSI and embedded systems. Embedded Systems: System-level design, HW/SW co-design, multi-core SoCs, embedded processor and memory design, networks-on-chip, defect-tolerant architectures, accelerators, FPGA and reconfigurable systems, firmware, middleware, parallelization, virtualization, real-time support, and case studies Security and Privacy: embedded systems security, hardware security, IP trust, physically unclonable functions, random number generators, fault tolerant systems and architectures, system security, side channel attacks and countermeasures
IoT and Cyber-Physical Systems: Internet-of-Things (IoT) devices, cyber-physical systems, sensors/actuators, displays, control systems, and design for safety and certifications in airborne, health care, automotive and IoT applications Digital Design: Logic and physical synthesis, place and route, clock tree design, timing and signal integrity, design for manufacturability and yield, power integrity, variation-tolerant design Design Automation Algorithms: Logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floor planning, and compaction), post route optimizations
Analog and Mixed Signal: Design of analog and mixed signal IPs, high-speed wired and wireless interfaces, low-power analog design, analog and mixed-signal modeling, synthesis and validation RF Design: RF IP design, low-power and high-speed RFICs, RF modeling and CAD simulation, RFIC technologies, circuits, devices, fabrication, testing, reliability, and packaging; synthesis and verification, noise analysis. Power and Energy: low-power design, low-power systems, wireless power delivery, Power analysis and estimation, optimization and low-power design, energy-efficient design, battery-aware design, thermal management, energy harvesting, approximate computing
CMOS Technology and Devices: Deep nanoscale CMOS devices, device modelling and simulation, multi-domain simulation, device/circuit-level reliability and variability Test and Verification: Simulation, formal verification, validation at different abstraction levels, DFT, fault modelling and simulation, ATPG, BIST, fault tolerance, post-silicon validation and debug, delay test, memory test, reliability testing

Emerging Technologies: Post-CMOS devices, MEMS sensors, biomedical circuits, lab-on-chip, carbon nanotubes, silicon photonics, spintronic, memristors, neuromorphic and quantum computing

SPECIAL ISSUES: Highest ranked papers from regular submissions will be tentatively (proposals under review) invited to thematic special issues in the IEEE Transactions on VLSI Systems, and the IET Computers & Digital Techniques.

BEST PAPER AWARDS: Top papers will be considered for the Best Paper Award, Best Student Paper Award, and Honorable Mention Award.

EMBEDDED TUTORIALS AND SPECIAL SESSIONS: Proposals in relevant emerging areas should be submitted as two-page abstracts. On acceptance, authors are required to submit full regular papers.

HALF-DAY AND FULL-DAY TUTORIALS: Tutorial proposals are invited in any of the above areas that would be exciting to the attendees.

PANELS: Proposals must be submitted with an abstract, and a list of panelists.

SUBMISSIONS: All submissions should be made electronically via the conference website by July 15, 2018. Your manuscript should clearly state the novel ideas, results, and applications of the contribution. Paper submissions will undergo a double-blind review. Papers must be in PDF format and not exceed 6 single-spaced pages including figures and references in two-column IEEE conference paper format (10pt font). Papers exceeding the page limit or identifying the authors will be rejected without review.

EXHIBITS: Please contact the Exhibits Chair to explore opportunities to display your products/services.

FELLOWSHIPS: The conference will award fellowships, based on need and merit, to partially cover expenses of attendees from India. Application details will be posted at the conference website.

DESIGN CONTEST: Please check the conference website or contact the Design Contest Chair for more details.

USER TRACK AND PHD FORUM: Please check the conference website for details on criteria and submission dates.

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