Ph.D. Forum Detailed Program

PhD Forum Detail Program
Day, Time, Location Thesis/Paper Start-End Title Author/s Affliation
Jan 8th, 11:55 – 1:15 Paper-24 11:55-12:06 A PAM-4 10S/12S line coding scheme with equi-probable levels Ron Joseph, Sandeep Goyal and Shalabh Gupta IIT Bombay, India
Thesis-38 12:06-12:28 Design and Implementation of Energy Efficient Transceivers for High Speed Data Link across On-chip Interconnects Nijwm wary and Pradip Mandal IIT KGP, India
Paper-4 12:28-12:39 Self Aware Nature Inspired Approaches Ensuring Embedded Security Krishnendu Guha Culcatta Univ., India
Thesis-1 12:39-1:01 Translation Validation of Optimizing Transformations of Programs using Equivalence Checking Kunal Banerjee IIT KGP, India
Paper-10 1:01-1:12 Power Characterization and Optimization of Content Addressable Memories and 3D Integrated Circuits Siddhartha Joshi and Seda Ogrenci-Memik North Western Univ., USA
  1:12-1:15 Certificate Distribution Ceremony – Session 1P
Jan 8th, 4:25 – 5:45 Paper-14 4:25-4:36 Understanding Drain Current Saturation and VDSAT Extraction in Tunnel FETs: Analog Design Outlook Abhishek Acharya, Sudeb Dasgupta
and Anand Bulusu
IIT Roorkee, India
Thesis-34 4:36-4:58 Design of OTA based Field Programmable Analog Array for Linear and Nonlinear VLSI Circuits Mousumi Bhanja and Baidyanath Ray IIEST Shibpur,India
Paper-18 4:58-5:09 Flip Around Second Order Sigma-Delta Modulator (M) Using Single OPAMP Vivek Sharma and Nithin Kumar Y.B. NIT Goa, India
Thesis-5 5:09-5:31 Variability Aware Design of Energy Efficient SRAM in Conventional & Non-Conventional MOS Technologies: A Sense Amplifier Perspective Bhupendra Reniwal, Santosh Kumar Vishvakarma IIT Indore, India
Paper-27 5:31-5:42 Test Time Reduction using Variable Rate Test Clocks in Many core SoCs Harikrishna Parmar and Usha Mehta Nirma Univ, India
  5:42-5:45 Certificate Distribution Ceremony – Session 2P
Jan 9th, 10:20 – 11:40 Paper-41 10:20-10:31 Design-For-Security/Trust Methodologies For Digital Integrated Circuits Rajit Karmakar and Santanu Chattopadhyay IIT KGP, India
Thesis-20 10:31-10:53 Frequency Synthesis for Cognitive Radio Receiver and other Wideband Applications Zaira Zahir and Gaurab Banerjee IISc Bangalore, India
Paper-49 10:53-11:04 On-Chip NBTI Sensor Circuits for Stable and Reliable CMOS Circuits Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar and Santosh Vishvakarma IIT Indore, India
Thesis-16 11:04-11:26 Repeaterless Low-Swing On-Chip Interconnects Naveen Kadayinti IIT Bombay,India
Paper-50 11:26-11:37 Adaptive NoC Routers for Congestion Management Abhijit Das IIT Guwahati, India
  11:37-11:40 Certificate Distribution Ceremony – Session 3P
Jan 10th, 10:30 – 11:50 Poster Display 10:30-11:50 All 9 (ID-4,10,14,18,27, 24,41,49 & 50) papers presented during track 1P,2P & 3P on Jan 8th & 9th will also be displayed as hard poster, Presenting author must be available next to his /her poster during this time slot
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