VLSI Design and Embedded Conference 2018
– Call for Papers

Submission of Regular Paper Deadline  :  Aug 7, 2017 (closed)
Submission for Tutorial Deadline    : Aug 27, 2017 (closed)
Notification of acceptance                :  September 17, 2017 (closed)
Camera ready paper due                  :  October 8, 2017 (closed)

Please submit your paper at Submission Link
Submit your tutorial Proposal at Submission Link
Download Call For Paper

Theme: Safe and Secure Intelligent Systems

Call for Papers


This joint conference is a forum for researchers and designers to present and discuss current topics in VLSI design, electronic design automation, embedded systems, and emerging technologies. Two days of tutorials will be followed by three days of regular paper sessions, special sessions, and embedded tutorials. Industry presentation sessions along with exhibits, panel discussions, Design Contest, and Education Forum round off the program. The conference is followed by the Reliability Aware System Design and Test (RASDAT) workshop.


TOPICS OF INTEREST: Papers are invited on previously unpublished results in the following categories:



E1: Embedded Systems Hardware: HW/SW co-design, SoC, multi-core systems, board level hardware, HW security, Internet-of-Things (IoT) devices, sensors/actuators, displays.

E2: Embedded Systems Software: Operating systems, firmware, algorithms, middleware, runtimes, parallelization, virtualization, software for low power, security, reliability, real-time support, emerging applications (e.g., automotive, telematics, analytics).

E3: FPGA and Reconfigurable Systems: FPGA architecture and FPGA circuit design, CAD for FPGA, FPGA prototyping, FPGA-based accelerators.

E4: Wireless Systems: Sensor networks, low-power wireless systems, wireless protocols, wireless power delivery.

E5: Embedded Case Studies: Practical and industrial tools, methodologies, designs in various application areas: wireless, medical, networking, multimedia, automotive, controls, etc.



T1: Design Verification: Functional, formal, coverage-driven, hardware-assisted, and assertion-based verification, behavioral, RTL, and gate-level simulation, emulation, equivalence checking.

T2: Test, Reliability, Fault-Tolerance: DFT, fault modelling and simulation, ATPG, BIST, repair, delay test, fault tolerance, online test, AIMS/RF test, board-level and system-level test, silicon debug, post-silicon validation, memory test, reliability testing.

T3: Computer-Aided Design(CAD)tools: Logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floor planning and compaction), post route optimizations.



M1: System-level Design: methodologies and architectures, processor and memory design, multi-core, GPU design, networks-on-chip, defect-tolerant architectures, accelerators, distributed system (e.g., automotive), cyber-physical systems.

M2: Advances in Digital Design: Logic and physical synthesis, place and route, clock tree design, timing and signal integrity, design for manufacturability and yield, power integrity, variation-tolerant design.

M3: Analog, Mixed-Signal and RF Design: Design of analog, mixed signal, and RF IP, high-speed wired and wireless interfaces, low-power analog and RF.

M4: Power-Aware Design: Power analysis and estimation, optimization and low-power design, energy-efficient design, battery-aware design, thermal management, energy harvesting.

M5: CMOS Technology and Devices: Deep nanoscale CMOS devices, device modeling and simulation, multi-domain simulation, device/circuit level reliability and variability.

M6: Emerging Technologies: Post-CMOS devices, MEMS sensors, biomedical circuits, lab-on-chip, carbon nanotubes, silicon photonics, spintronic, memristors, neuromorphic and quantum computing.



S1: Design for Safety and Relibility: Physically unclonable functions, random number generators, fault tolerance systems and architectures.

S2: Secure Circuits and Systems: System security, side channel attacks and anti-piracy methodologies, Embedded systems security in healthcare, automotive, industrial and IoT applications.

S3: Safety Assurance of Circuits/ Systems: Design for functional safety and certifications in airborne, health care, automotive systems.


EMBEDDED TUTORIALS AND SPECIAL SESSIONS: Proposals in relevant emerging areas should be submitted as two-page abstracts. On acceptance, authors are required to submit full regular papers.

PANELS: Proposals must be submitted with an abstract, and a list of panelists.

SUBMISSIONS: All submissions should be made electronically via the conference website by July 16, 2017. Your manuscript should clearly state the novelideas, results, and applications of the contribution. Paper submissions will undergo a double-blind review. Papers must be in PDF format and not exceed 6 single-spaced pages including figures and references in two-column IEEE conference paper format. Papers exceeding the page limit or identifying the authors will be rejected without review.

EXHIBITS: Please contact the Exhibits Chair to explore opportunities to display your products/services.

FELLOWSHIPS: The conference will award fellowships, based on need and merit, to partially cover expenses of attendees from India. Application details will be posted at the conference website.

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