VLSI Design
VLSI Design

call for paper

Research papers are invited on previously unpublished results in the following categories:

Embedded Systems:
Embedded system hardware/software co-design; Reconfigurable hardware design; Embedded software; Real-time operating systems; Middleware and virtualization; Embedded multi-cores and many-cores; Communications; Encryption, security, compression; Hybrid systems-on-chip; Sensor networks; Programmable devices; Hardware-software co-verification; Embedded system reliability; Embedded applications (automotive, mobile, medical, etc.), platforms, and case studies
Digital Design:
Low-power design; Asynchronous design; Package and board design.
Analog/RF Design :
Low-power design; Analog, mixed-signal, and RF systems; Package and board design.
System-level Design/ESL:
System-level design methodology; Gigascale design methodology; Multicore systems; Processor and memory design; Concurrent interconnect; Networks-on-chip; Defect tolerant architectures.
Logic Synthesis and Physical Design:
Logic synthesis; Technology mapping; Asynchronous synthesis; Physical design; Floor planning; Placement; Routing; Clock Design; Layout issues in design for manufacturability.
Test and Reliability:
Fault modeling/simulation; ATPG; DFT; Delay test; Fault-tolerance; Online test; AMS/RF test; Board-level and system-level test; Silicon debug, post-silicon validation; Memory test; Reliability test.
Functional Verification:
Behavioral Simulation; RTL Simulation; Coverage Driven Verification; Assertion Based Verification; Gate-level simulation; Emulation; Hardware Assisted Verification; Formal Verification; Equivalence Checking; Verification Methodologies.
Device/circuit simulation and modeling:
Design verification; Signal integrity; Technology modeling-design-simulation; Analog/mixed-signal simulation; Multi-domain simulation; Numerical methods; Device modeling; Timing analysis; Asynchronous timing; Device/circuit level variability models; Reliability simulation.
Emerging Technologies:
Issues in nano-CMOS technologies; MEMS; CMOS sensors; CAD/EDA methodologies for nanotechnology; Non-classical CMOS; Post-CMOS devices; Biomedical circuits and systems.
All submissions should be made electronically via the conference website by 24th July, 2013. Your manuscript should clearly state the novel ideas, results and applications of the contribution. Paper submissions will undergo a double-blind review. Papers must be in PDF format and not exceed 6 single-spaced pages including figures and references in two-column IEEE conference paper format available here. Papers exceeding the 6 page limit or identifying the authors will be rejected without review.

All submissions of papers and proposals will imply that, if selected, they will be presented at the conference in person. Hence, approvals from parent organizations must be obtained before the submissions are made.

important dates

Submission deadline : Closed

Due Date for Full Paper Submission : Closed

Notification of acceptance : 4th October, 2013

submission site

Submission Closed
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