VLSI Design
VLSI Design

User/Designer Track Program Schedule


This is the Tentative Schedule

Invited Speaker - C.Srinivasan, Cosmic Circuits, "Evolution of Mixed Signal Design"
January 7, 2013 (12:00 pm - 1:20 pm)

C Srinivasan

 

 

Abstract :- This talk will focus on the evolution of Mixed signal design in DSM. As the process features shrink, some of the aspects of mixed signal designs have become easier and some harder.


The evolution of architectures in data converters, PLLs, Power circuits , connectivity etc will be highlighted  with focus on the digitally assisted analog circuits. The availability of high BW xtors albeit at lower voltages tolerances help tradeoff accuracy and speed. Architectures that take advantage of these will be touched upon. Concerns on reliability and  techniques to address some of these will be addressed.


Speaker Biography :- C.Srinivasan received his B.Tech in Electronics and Communications from IIT Chennai in 1989 and M.S from IIT Chennai in 1996. His work experience includes setting up a Startup, Cosmic Circuits, 14 years in TI in the mixed signal design group and 1.5 years in HCL Technologies working on board level solutions. In his 14 years of association with TI, he worked in a variety of fields. Starting with Analog modeling, he then led a team to develop data converters. His team was responsible to putting TI in a leadership position on the SAR ADC products with resolutions up to 18bits and speeds up to 1MSPS.  Subsequently he led a team to develop WLAN chips. His team was responsible for the full digital implementation of the PHY and MAC layers as well as communication algorithm development.

 

In 2005, he co-founded Cosmic Circuits focusing on Analog and Mixed Signal designs. As VP Engineering, he has setup the team to execute a variety of analog IPs including Power Managements chips, Data Converters, Analog Front Ends, PLLs, Serial Interfaces, Analog ASICs etc.  He has authored 3 international papers and 5 patents in his name.

 




User Track 1 - DFT : Session Chair: Rajagopalan Srinivasan
7th January 2013 (2:20 pm - 3:40 pm)

Novel DFT architecture for multi-core SoCs enabling modular IDDQ
Arvind Jain, Pradeep P and Sachin Badole, TI India

Test Time Reduction of a Pin Limited Large Hierarchical MultiPower Domain SoC Architecture
Ajay Dimri, Rudraksha Dani and Shiv Kumar Vats,
ST Microelectronics Ltd


At-Speed Delay Testing of IOs using existing IEEE 1149.1 TAP Architecture
Mudasir Kawoosa and Rajesh Mittal, TI India


Efficient Test Clocking Structures and Techniques for Transition Fault Testing of SoCs with Multiple Clock Domains
Rajesh Mittal, Prakash Narayanan, Puneet Sabbarwal, Surya Samavedam, Sujit Tikekar and Charles Kurian, Texas Instruments




User Track 2 - Pot Pourri (Mixed Signal/Reliability/Design Closure) : Session Chair : Dhanendra Jain

7th January 2013 (4:50 pm - 6:10 pm)

Zero defect Mixed Signal SoCs
Kushal Kamal, Sunny Gupta and Kumar Abhishek, Freescale

On-chip LDOBIST for Extremely Low Cost Test of Voltage Regulators in Mixed Signal SOCs with Integrated Power Management
Rajesh Mittal, Puneet Sabbarwal and Harikrishna Parthasarathy, Texas Instruments, India

HoS: A metric driven approach to measure Quality/Health of Silicon
Manish Verma, AnilKumar SeshagiriRao and Shivaprasad Sadashivaiah, Infineon Technologies India Private Limited

Do-Different design closure techniques for multimedia application processor System-On-Chip for wireless, Mobile Internet Device and consumer market
Naishad Parikh, Vivek Pai, Anubhav Shukla, Sharad Arora and Ajay Shah, Texas Instruments



Invited Speaker - Satish Soman, Atrenta  " Global Design Closure "

January 8, 2013 (11:00 am - 12:20 pm)


 


Abstract :- Today’s SoC designs integrate complex heterogeneous IPs/Subsystems. These IPs are concurrently developed in different geographies. Physical design issues ( like congestion etc) of these complex IPs ( and their interactions) many times remain latent till final SoC enters physical design cycle. Late discovery of these issues causes long and unpredictable iterations in the physical design of the IP as well as SoC. This talk provides further insight into the nature of this problem and requirements of solutions. Current approaches in the industry are also discussed.

 

Speaker Biography :- Satish has over 30 years of experience in Chips and System Design. His expertise spans Architecture, Logic Design, Verification, Validation and field support of ASIC/COT designs. He has successfully delivered 18 production designs in the areas of Computing, Multimedia and Networking domains.  He has held executive management positions at DEC, LSI Logic, Axiowave and Lucent. He was co-founder of Nexabit  (acquired by Lucent).  He is also on advisory boards of few start-up companies. Satish holds 16 patents. He has published papers in leading technical journals and conferences
       He holds MS in Computer Engineering from Syracuse University and B.Tech in Electrical Engineering from IIT-Bombay



User Track 3 - System level Design/ESL : Session Chair : Sagar Khedkar

8th January 2013 (1:20 pm - 2:40 pm)

A modular approach for achieving SOC level Gate simulation verification
Sundeep Gupta, Shriprasad Lokare, Applied Micro

Clock Abstraction & Event Synchronization For Infiniband Mutli lane Link-Layer Using Transaction Level Modeling
Chaitanya Naik and Himanshu Rawal, Intel India Pvt Ltd

System Verilog DPI Based SOC simulation environment reuse for Verification, Validation and FPGA
Nisreen Taiyeby, Pushkar Naik, Shailendra Chavan, Jayant Kurkure. Applied Micro

Virtual Platforms for System Debugging and Analysis
Praveen Wadikar, Cadence Design Systems




User Track 4 - Functional Verification : Session Chair : Srini Venkataramanan

8th January 2013 (3:45 pm - 5:05 pm)

UVM and Integration of Legacy Methodologies
Amit Sharma and Santosh Sarma, Synopsys India, Wipro

Next Generation Verification Approach - OVM-VMM Interoperability
Vignesh Manoharan, Cypress Semiconductors

Addressing IP Integration Challenges at Functional Verification Level
Pusuluri Venkata Giri Kumar, Kamlesh Ram Raiter, Devashish Dutta, Naveen Kumar Korada and Spurthi B, Synopsys India Pvt Ltd

Accelerating CDC Verification with SDC setup
Ashish Hari and Yogesh Badaya, Mentor Graphics




User Track-5 - Physical Design Closure : Session Chair: Arvind Shrivastava

9th January 2013 (11:00 am - 12:20 pm)

Staircase non-rectangular macros and related design challenges
Adarsh Subramanya, Gary Gorman and Daniel Lewis, IBM Processor Division, India

Optimal Placement of Spare Flip Flop circuitry in high performance processors
Ayan Datta, Charudhattan Nagarajan, Vijay K Ankenapalli and Sumitha George, IBM India

Using fast, high-capacity, attofarad-accurate 3D extraction for successful design of high performance IPs in advanced CMOS nodes
Atul Bhargava, Srisurya Konduri, Chittoor Parthasarthy, Jean Claude Marin and Claudia Relyea, STMicroelectronics, India

Impact of Package and On-Die Power Distribution Network on the relative performance of individual Cores in a multi-Core SoC
Kannan N and Gagan Kumar, Freescale.




User Track 6 - Pot Pourri (Low Power, Power Integrity, STA) : Session Chair: Yash Punati

9th January 2013 (1:20 pm - 2:40 pm)

Validation and Debugging Techniques for Statistical Timing Analysis
Sachin Shrivastava, Cadence Design Systems

A Case-study of Production Debug of At-Speed Silicon Failures Using Low Power ATPG Techniques Nayana
Prakash, Sanjay HV, Venkatraman Ramakrishnan, Srivaths Ravi and Krishna Chakravadhanula, Texas Instruments, India

EDA Challenges in Utilizing AOCV STA to Minimize Design Margins for Signoff and Optimization
Sreeram Chandrasekar, Sourav Banerjee and Nagabharana Teeka, Texas Instruments India

Energy Estimation at multiple abstraction levels in a wireless baseband processor design
Prabhat Avasare and Martin Palkovic, IMEC, Belgium




User Track 7 - Design Methodologies and Tool Flows : Session Chair: Jayendra Dwaraka

9th January 2013 (3:45 pm - 5:05 pm)

100 Gb Ethernet Tributary Interface Module Card for OTN DWDM platform, From Concept to Production
Kiran Kapshikar, Manish Verma, Ravi Tangirala and Tulasi Veguru, Infinera

Zero Simulation Verification Flow For SOC Using Formal Verification Techniques
Garima Srivastava, Kushagra Garg, Subir Roy, Debmalya Lahiri and Bijitendra Mittra, Texas Instruments, India

SCONE – Smaller Cone debugging technique based on divide and conquer to diagnose complex failures in equivalency check
Aman Jain, LSI India

Custom Datapath Synthesis Methodology for High-Speed Microprocessor Design
Sourav Saha and Charudhattan Nagarajan, IBM Processor Division, India



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